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Thu, 23 May 2013 08:20:00 +0100
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Thu, 23 May 2013 08:09:00 +0100
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Thu, 23 May 2013 01:33:00 +0100
QUITO -  An Ecuadoran satellite launched last month could collide with the remains of a Russian rocket in the coming hours, the country's civilian space agency warned Wednesday. The "Pegaso" (Pegasus) nanosatellite, designed and built in Ecuador, set off aboard an unmanned rocket April 25 from the Jiuquand station in northern China. It is the country's first. "Alert: possible collision between NEE-01 Pegaso and Russian rocket remains," tweeted the country's civi...
Tue, 21 May 2013 16:52:00 +0100
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Tue, 21 May 2013 10:00:00 +0100
When did the first stars and galaxies form in the universe? How brightly did they burn their nuclear fuel? Scientists will seek to gain answers to these questions with the launch of the Cosmic Infrared Background ExpeRIment (CIBER) on a Black Brant XII suborbital sounding rocket between 11 and 11:59 p.m. EDT, June 4 from the Wallops Flight Facility in Virginia. Jamie Bock, CIBER principal investigator from the California Institute of Technology, said, “The first massive stars to...
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    CV: ASIC / FPGA Designer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
     Mobile:<withheld>
    Candidate Profile
     Date Submitted:17-02-2010
     Last Modified:17-02-2010 (08:54)
    Job information
     Current job:ASIC / FPGA Designer
     Employment Term:Permanent
     Job location:Europe only
     Date available:
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators
     KeywordsASIC FPGA
    CV

    Degree in Electronic Engineering (Laurea in Ingegneria Elettronica), Italy, 1998

    Professional experience:

    Sept. 1998 to April 1999: Internship in a leading company of space industry, Italy, in prosecution of his Thesis, previously developed in the VLSI design center of the same site.

    May 1999 to Sept. 2000: Employed in a leading company of automotive industry, Italy, as Technical Services Team project leader. He was involved in engineering projects for production automation (PLC’s and motion controls), in the Predictive Maintenance Program implementation, and gained the Six Sigma Green Belt.

    Oct. 2000 up till now: Employed in a leading company of space industry, Italy, as ASIC and FPGA designer in the VLSI design center. Starting September 2006 till April 2007 he worked in a French site of the same company.

    Professional skills:
    • Hardware Description Languages: VHDL;
    • Development tools: HDL Designer;
    • Simulation tools: Modelsim;
    • FPGA synthesis tools: Synplicity, ACTEL Designer, Altera Quartus;
    • ASIC synthesis tools: Synopsys;
    • Software Languages: Matlab.

    Foreign languages:
    • English: very good level (written, read and spoken);
    • French: very good level (written, read and spoken);
    • Spanish: intermediate level;
    • German: basic level.
     


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