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Thu, 18 Dec 2014 08:19:00 +0100
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Wed, 17 Dec 2014 17:00:00 +0100
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Wed, 17 Dec 2014 14:00:00 +0100
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Wed, 17 Dec 2014 12:00:00 +0100
This spectacular image of the star cluster Messier 47 was taken using the Wide Field Imager camera, installed on the MPG/ESO 2.2-metre telescope at ESO's La Silla Observatory in Chile. This young open cluster is dominated by a sprinkling of brilliant blue stars but also contains a few contrasting red giant stars. Messier 47 is located approximately 1600 light-years from Earth, in the constellation of Puppis (the poop deck of the mythological ship Argo). It was first noticed some time before 1...
Wed, 17 Dec 2014 07:51:00 +0100
Soyuz Flight VS10 Arianespace's next medium-lift Soyuz to be launched from French Guiana is now complete following the integration of its "upper composite," which consists of four O3b Networks connectivity satellites, their protective payload fairing and the Fregat upper stage. This activity was performed at the Spaceport's ELS launch complex. It began with the upper composite's transfer from the S3B payload preparation facility to the launch pad on a special transporter, and was followed ...
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    CV: ASIC / FPGA Designer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
     Mobile:<withheld>
    Candidate Profile
     Date Submitted:17-02-2010
     Last Modified:17-02-2010 (08:54)
    Job information
     Current job:ASIC / FPGA Designer
     Employment Term:Permanent
     Job location:Europe only
     Date available:
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators
     KeywordsASIC FPGA
    CV

    Degree in Electronic Engineering (Laurea in Ingegneria Elettronica), Italy, 1998

    Professional experience:

    Sept. 1998 to April 1999: Internship in a leading company of space industry, Italy, in prosecution of his Thesis, previously developed in the VLSI design center of the same site.

    May 1999 to Sept. 2000: Employed in a leading company of automotive industry, Italy, as Technical Services Team project leader. He was involved in engineering projects for production automation (PLC’s and motion controls), in the Predictive Maintenance Program implementation, and gained the Six Sigma Green Belt.

    Oct. 2000 up till now: Employed in a leading company of space industry, Italy, as ASIC and FPGA designer in the VLSI design center. Starting September 2006 till April 2007 he worked in a French site of the same company.

    Professional skills:
    • Hardware Description Languages: VHDL;
    • Development tools: HDL Designer;
    • Simulation tools: Modelsim;
    • FPGA synthesis tools: Synplicity, ACTEL Designer, Altera Quartus;
    • ASIC synthesis tools: Synopsys;
    • Software Languages: Matlab.

    Foreign languages:
    • English: very good level (written, read and spoken);
    • French: very good level (written, read and spoken);
    • Spanish: intermediate level;
    • German: basic level.
     


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