OBJECTIVE

To obtain a challenging full-time R&D position in the field of electrical engineering, specializing in the design of communication systems

PROFESSIONAL SKILLS

• Communications systems Knowledge: comprehensive understanding of communication system structure and algorithms, knowledge of ADSL, VDSL and WiFi 802.11n systems
• Knowledge of Digital signal processing, communication, estimation theory, DSP architecture and efficient algorithm implementation on DSP
• Programming Skills: C, MATLAB, C++ and assembly language of Globespan multi processor architecture and general purpose DSP - Motorola 56300 and other
• Ability to rapidly go deep into implementation details and generate new ideas of advanced debugging techniques using Test equipment, such as spectrum analyzer digital Oscilloscope and Logic Analyzer
• Good communication skills, mentoring other people, team worker and team leader ability

WORK EXPERIENCE

Oct 2007 – Present                            Metalink broadband access

DSP Engineer

• Participate in the development of a next generation WIFI 802.11n modem PHY layer – including all critical blocks in the wireless OFDM MIMO 4x4 system: MIMO equalizer, MIMO decoder (ML, sphere, Linear), channel estimation, channel tracking, phase estimation and tracking, space time coding, Frequency domain timing scheduling, time domain processing – AGC, frequency estimation, timing estimation and RF module calibration.

• Participate in designing advanced 802.11n features like explicit/implicit beamforming for performance improvements
• Participate in Wifi MIMO system design and implementation
• Took responsibility of specification, simulation and implementation of two blocks – Channel tracking block and phase tracking block
• Redesigned channel tracking block to save 80% of the block area
• For both channel tracking and phase tracking blocks, write detailed specs and include the blocks in Matlab simulation and C++ fix point simulation
• Generate test vectors from C++ simulation to test the VLSI implementation

Jan 2000 – Oct 2007                          Globespan Semiconductor/Conexant

VDSL Technology Technical Leader of FW Development

• Technical leader of Central Office VDSL2 firmware team to implement VDSL2 five bands modem on third generation VDSL2 Chipset developed in Conexant system. This includes chip/board initial bring up, algorithms refinement, DMT/OFDM FW architecture design implementation and firmware/hardware debugging of five bands VDSL2 system.
• Designed and debugged Analog front end chip controlled by firmware for improved system performance and robustness like auto mode selection algorithm, improved startup signaling, tone selection and VDSL2 digital duplexing synchronization. Also developed test plans to cover different aspects of VDSL2 phy layer functionality before releasing the firmware to customers.
• Worked with a group from china to mentor the group to achieve the goal of developing and supporting next generation VDSL2 Customer Premises Equipment in the topics of timing recovery, analog/digital performance optimization, code architecture, system mode selection and processing distribution between multiple DSP cores
• Group technical leader of VDSL2 FW team to design and implement VDSL2 modem on second generation CO Chipset developed in Conexant system.  This includes VDSL2 algorithms – frame alignment, equalization, timing recovery and bit loading optimization.

o        Responsible for performance optimization for the new chip structure and leading interoperability effort with other vendors

• Technical lead for a multi-core DSP modem architecture design and implementation of the first Quad bandwidth DMT ADSL++ system with rates up to 50/10Mbps including over samples complex discrete multi tone modulation to achieve necessary band width definition with in chip limitation
• Technical lead on a multi-core DSP modem architecture design and implementation of the first double bandwidth ADSL+ DMT system that supports rates up to 28/1Mbps and multi mode transition between ADSL1 and ADSL+
  • Included Analog front end optimization for ideal performance
• Detailed design of a non-standard, very high speed symmetric transceiver using existing Globespan multi-core architecture
• Initial detailed design of a DMT standard VDSL transceiver using existing Globespan’s multi-core architecture
• Generation of online (sample by sample) simulation for standard VDSL single carrier based on Simulink platform
• Updated DSL performance simulation platform for VDSL support

1993 – 1999                                         ECI Telecom, Israel

DSP Technical Group Lead

• 1997-1999:  DSP technical group leader of 4 DSP programmers for development of ADSL CAT2 modem Prototype in cooperation with Siemens semiconductor team in Austria
• Participate in the ADSL CAT2 C simulation structure definitions, algorithms development and implementation
• Full responsibility for ADSL CAT2 Matlab offline simulation including AFE (Analog front end) chip simulation and optimization, integrated with the digital algorithms of combined time domain - frequency domain DMT Echo cancellation, digital filtering, Equalization and DMT modulation and demodulation
• 1996-1997:  Simulation and implementation of Metallic line tester for Telephone lines, using match filters and optimum line parameters estimation. DSP 56002 code development
• 1993-1996: Implementation of ADSL CAT1 system on Multi DSP 56301 board
• ADSL Matlab offline simulation development includes Analog and digital path simulations, time and frequency domain Equalizers initialization Algorithms, Bit allocation and energy allocation Algorithm based on SNR estimation
• ADSL C-simulation development and integration based on the Matlab offline simulations includes also additional implementation of Encoder, decoder, modulator demodulator, timing recovery and synchronization symbol
• Implementation of the C- simulation functionality on 56301 Multi DSP  board

PUBLISHED PATENTS

System and method for applying transmit windowing in ADSL+ networks (appears as part of the ADSL2+ standard) - Rapaport, Albert; 7,190,731

PENDING PATENTS

• MIMO dynamic PSD allocation for DSL networks - Langberg, Ehud; Scholtz William; Cai, Lujing; Rapaport, Albert; Rahman, Shareq; Duvaut, Patrick;
• Method and system for enhancing bit rate in DMT quad spectrum systems - Barak, Ehud; Rapaport, Albert
• Method and system for selecting an optimal asymmetric digital subscriber line mode - Rapaport, Albert
• Method and system for mitigating fourier transform side lobes - Duvaut, Patrick; Langberg, Ehud ; Rapaport, Albert ; Sholtz, William; Shmulyian, Faina;

EDUCATION

MSEE (incomplete), Tel-Aviv University, 1996 – 1999

• Passed all MS courses but did not finish thesis due to relocation to US

BSEE, Ben-Gurion University, 1989 – 1993

• Top graduate

PROFESSIONAL COURSES

• 2007: Management Course in Conexant system
• 2004: Advance digital communication by Prff. Callet
• 1998: Managing Course in ECI telecom
• 1998: Wireless LAN by LOGTEL
• 1994: Digital Communication by Prof. R.D Gitlin

MILITARY SERVICE

1985-1989: Electronic technician at the Air Force unit

STATUS

US permanent resident - Hold US green card. Now in process for US citizenship.

References Available Upon Request