CV: Satellite/Network Specialist

OBJECTIVE: Seeking a position in Electrical Engineering/Satellite Communication

EDUCATION: Polytechnic University, Brooklyn, NY Polytechnic University, Brooklyn, NY Masters of Science in Electrical Engineering Bachelor of Science in Electrical Engineering Expected Graduation: June 2009 Graduated: December 1999

SECURITY CLEARANCE: Active Secret

CERTIFICATES:
• Secure Mobile Anti-Jam Reliable Tactical-Terminal (Smart-T) Specialist
• Cisco CCNA/CCVP
• Network Switching Systems Specialist

EXPERIENCE: DataPath Inc, Duluth Georgia, 08/07-Present, Site Lead/SatCom/Network Contractor: ;
• Responsible for over $2 Million worth of Satellite Communication Equipments
• Ensure the installation, operation, maintenance, performance of Ku-Band Mobile Terminals Antenna Controller, Satellite Acquisition, High Power Amplifier, LNA/LNB FDMA/TDMA modems (satellite modems), E-100 TACLANES, ViaSat Linkway Modems Solid State Power Amplifiers, Up-converters, down-converters, WPPL Systems, Raid Array Servers
• Troubleshoot and resolve any identified circuit or equipment outages or degradation

EXPERIENCE: US ARMY EUROPE, Darmstadt, Germany 03/05-03/08 JNN/Data Packet Specialist:
• Installs, Operates, and performs systems maintenance on Large/Small Electronic Switches Control Centers, Node Management Facilities, Combat Net Radio and line of Sight Radios
• Configure, Install, and Operate Promina 400/800, Paragain Modems, NRZ Converters, KIV 7/19 E-100 NSA Type-1 TACLANE, Small Extension/Large Extension Node Centers, Fiber Optics

EXPERIENCE: AMI Semiconductor, Andover, MA 01/01-02/02 ASIC Design Engineer Contractor:
• Participated in all phase of ASIC design methodologies (RTL to Mask Generation)
• Prepare, translate, debug, and convert customer netlist to AMIS’s ASIC conversion flow
• Responsible for closing timing based on the static timing analysis constraints provided
• Generate test vectors using ATPG (Synopsis) to verify simulation, solve, bug problems in circuit
• Perform Insert-scan technique into design to improve fault coverage and testability
• Use JTAG Boundary Scan methodology to characterize board traces for design
• Guide customer in circuit design and oversee transfer of new circuits into production

EXPERIENCE: Panasonic Semiconductor, Cupertino, CA 12/99-01/01 ASIC/FPGA Design Engineer Contractor:
• Write script files to perform synopsis’ FPGA synthesis flow through Tapeout
• Use Signal Scan and Debussy waveform viewer to debug and solve synthesis problems
• Map USB1.1 Core to Virtex (XCV300 BG432) and perform complete FPGA flow, perform Place and Route, verify gate-level simulation (Verilog RTL codes was already available for USB1.1 Core)
• Map ATAPI Bridge to Virtex (XCV300 BG432) perform complete FPGA flow, perform Place and Route, and verify gate-level Simulation. (Verilog RTL codes was already available for ATAPI Bridge)
• Write Top Level RTL codes (Verilog) to combine USB1.1and ATAPI Bridge, Verifies RTL simulation
• Map USB1.1/ATAPI Bridge to Virtex (XCV300 BG432); perform Place & Route, verify gate-level Accomplishments: Tape out USB 1.1/ATAPI Bridge, Complete FPGA synthesis for USB 2.0/ATAPI Bridge designs

ACTIVITIES: Member, Institute of Electrical and Electronics Engineer, Inc. (IEEE)