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  • CV: Real-time Embedded Software Engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:15-06-2011
     Last Modified:22-09-2011 (04:16)
    Job information
     Current job:Real-time Embedded Software Engineer
     Employment Term:Permanent
     Job location:Anywhere
     Date available:immediately
     Industry:Satellite Manufacturers and Subcontractors, , , Consulting/Engineering Services
     KeywordsReal-time Data Systems Engineer, Embedded System Software and Modeling, (Automatic) code generation, Good Communication and interpersonal skills, Ability to work in a team and to coordinate it
    CV

     

    REAL-TIME EMBEDDED SOFTWARE ENGINEER

    CORE COMPETENCIES

    Real-time Data Systems Engineer, Embedded System Software and Modeling, (Automatic) code generation.

    Space Application

    Real-time embedded systems – On Board Computer (OBC) architecture – Failure Detection Isolation Recovery (FDIR) – Reliability, Availability, Maintainability and Safety (RAMS) requirements – Dependability means (e.g., nominal/redundant blocks, hot/cold redundancy, cross-strapping)

    Code generation

    SystemC/C++ to VHDL (Catapult C Synthesis) – Simulink/MATLAB/Stateflow to HDL  (Simulink HDL Coder™) – SDL to FSM – SDL to C (Real Time Developer Studio) – UML modeling to C++ – ASN.1 to C – CORBA middleware and IDL to C

    Automated Testing

    JUnit and xUnit family frameworks – Ad-hoc tool for test-benches for VHDL architectures – TetraMAX™ Automatic Test Pattern Generator (ATPG) by Synopsys

    Analysis

    GNU DeBugger (GDB) – Data Display Debugger (DDD) – PostMark, Bonnie, Fstress Benchmarks

    Others

    Source Navigator – Doxygen

     

    RELEVANT EXPERIENCE

    I am currently performing a Visiting Scientist activity at European Space Agency (ESA), within the PhD framework in System and Computer Science Engineering. During my PhD, I had the chance to do several widespread activities like teaching, publishing (papers and a book chapter), attending international conferences, interacting with company managers (e.g., Thales Alenia Space), presenting and discussing my work in front of a broad knowledge audience. Furthermore, during the period at ESA, I dealt with both development and project management issues, providing effective support to ESA’s contractor companies. These experiences (and many others) were essential in developing my communication and interpersonal skills.

    I have a sound knowledge in space on-board architectures and in RAMS analysis. I am well-versed in different kind of code generation tools. I have deep experience in powerful frameworks for automatic generation of test cases and I am skilled in code analysis, benchmarking, partitioning and documentation.

    I am able to think out of the box and to quickly grasp and depict a (functional) system overview. I am skilled in analyzing software for inspecting/debugging purposes. Personally, I am curious and active, able to quickly fill knowledge gaps. I absolutely like to work in a team and, if needed, to coordinate it, being able to work under pressure and to meet deadlines.

    EMPLOYMENT HISTORY

    Visiting Scientist (ESA – ESTEC)

    March – November 2011 (Noordwijk, THE NETHERLANDS)

    Effective support to the "Latch up protection for COTS memories in space" ESA activity under contract no. 22866/09/NL/AT. Design and test of a memory bank IP embedding dependability means with multiple failure tolerance.

    Evaluations are performed according to specific RAMS requirements. Proper space system functional modes were identified, while the applied knowledge of safety and RAMS analysis led to the definition of proper Failure Detection Isolation Recovery (FDIR) methodologies – Error Correcting Codes (ECC) design via powerful C/C++ code generation tools and MATLAB Simulink HDL Coder. Implementation on RASTA 6x SpaceWire Router by Aeroflex Gaisler, baseline space-like implementation of a non volatile mass memory for the Modular Advanced Mass Memory Architecture (MAMMA) – RTEMS device driver development with RTEMS cross-compiling chain and RASTA environment.

    Digital System Design and Dependability Lecturer

    September 2009  – December 2010 (Torino, ITALY)

    Deep Expertise in Tetramax™ by Synopsys, an advanced automatic test pattern generator (ATPG).

    Computer Science Additional Classes Lecturer 

    February – June 2010 (Torino, ITALY)

    Deep expertise in C/C++ Programming Language at Politecnico di Torino.

    Telecommunication and Automatic Control Teacher

    February 2009 – April 2010 (Torino, ITALY)

    Teaching experience within the worldwide audience of the military environment. At the end of the course, candidates were able to deal with applied mathematics, to manipulate signals and to deal with technology for military applications.

     

    Real-Time Software Engineer

    Metoda Spa & Chibilogic ®, Via Ammaturo 124 – Avellino – Italy

    September 2007 – August 2008 (Avellino, ITALY)

    Design and Implementation of a Smart Card "Key Opener" based on a Microchip™ PIC16F84 micro-controller. Model checking techniques were applied to a finite model of the device. An exhaustive automata state space search (i.e., state space enumeration) was performed to formally verify the “Key Opener”. Furthermore, simple observersof safety properties were implemented, taking the device I/O and deciding whether the property is violated. Finally, knowledge and direct (human and professional) experience with the upcoming ChibiOS/RT RTOS for embedded applications.

     

    EDUCATION

    PhD Candidate

    in collaboration  with European Space Agency, Thales Alenia Space

    January 2009 – December 2011

    Torino, ITALY

    Politecnico di Torino – Dipartimento di Automatica e Informatica (DAUIN)

    Corso Duca degli Abruzzi, 24 – 10129 Torino – Italy – www.polito.it

    Currently working on the dependability assessment of flash memories for space applications. Evaluations are performed adopting reliability prediction (e.g., Mean Time Between Failures), Burn-in Analysis (e.g., stress tests until End-Of-Life of the device) and also fault-modeling techniques. On the one hand, UML description of a Flash Translation Layer (FTL) is adopted to automatically generate C++ code for implementation and integration inside commonly used RTOS (e.g., eCos). On the other hand, Data Display Debugger and Source Navigator were adopted to thoroughly analyze and partition Yet Another Flash File System (YAFFS) in a generic architecture made of functional blocks (FLARE). State-of-the-art benchmarking tools (PostMark, Bonnie, and Fstress) were adopted to assess different implementations of such blocks. Doxygen was exploited to produce meaningful documentation of the proposed architectures. Furthermore, a C-based ad-hoc framework automatically generates specific Error Correcting Codes (ECC) architectures. Test-benches code generation, aimed at automated testing, was performed for the generated ECC architectures.

     

    Computer Science Engineering Master Degree

    January 2007 – December 2008 (Napoli, ITALY)

    Università degli Studi di Napoli "Federico II", Piazzale Tecchio 80 – 80125 Napoli – Italy – www.unina.it

     

    Final Mark

    110  / 110 summa cum laude

    Thesis

    “Flash memory for Space Applications: Testing and Reliability”

     

    Comprehensive overview of On Board Computer (OBC) architecture. Reliability, Availability, Maintainability and Safety (RAMS) requirements analysis. Development of fault tolerant architectures (e.g., TMR, ECC, hot-cold redundancy, cross-strapping). Simulations, error injections and scenario validation against requirements.

     

    Computer Science Engineering Bachelor Degree

    September 2003 – December 2006 (Napoli, ITALY)

    Università degli Studi di Napoli "Federico II", Piazzale Tecchio 80 – 80125 Napoli – Italy – www.unina.it

    Final Mark

    110  / 110 summa cum laude

    Thesis

    “Embedded System Development on a FPGA Hardware”

     

    Work on the Virtex-4 FPGA Xilinx University Program (XUP) development board. LEON2 and LEON3MP processors together with the uClinux OS represented the resulting powerful development framework.


    LANGUAGE SKILLS

     

    Reading Skills

    Writing Skills

    Speaking Skills

    ITALIAN

    Mother Tongue

    Mother Tongue

    Mother Tongue

    ENGLISH

    Excellent

    Excellent

    Excellent

    FRENCH

    Good

    Basic

    Good

    Certificate: International English Language Testing System (IELTS) with Mark  7.0

     

    SOCIAL SKILLS AND COMPETENCES

     

    Member of Board of European Students in Technology (BEST) Napoli

    http://www.best.eu.org/, http://www.bestnaples.altervista.org/

    April 2007 – Today

    Napoli, ITALY

     

    Treasurer and Corporate Relation Responsible of BEST Napoli 07-08 – Organizer of four educational/leisure courses from 2007 to 2010 – Organizer of Italian BEST Engineering Competition (iBEC) 2008 – Organizer and Speaker of "How to deal with the companies?" (Napoli, 19th Apr. 2008) – Organizer and speaker of ISO 9001:2000 Course in 2007 – Organizer of Photo Contest 2007 – Organizer and participant of Cultural Exchanges with LBG Porto (Portugal), Tallin (Estonia) and Paris École Polytechnique (France) in 2008 – Trainings in “Conflict Solving” (Tallinn, 4th May 2008), “Project Management” (Paris, 18th Oct. 2008) – Workshop “Looking for something excellent?” by Bekaert (Tallinn, 27th Apr. 2008)

    AWARDS

    HiPEACnetwork of excellence (Grant Agreement no ICT-217068)

    Collaboration grant funded by the HiPEAC Network of Excellence for the “Dependability Assessment of NAND Flash Memory for Space Applications” at the European Space Agency (ESA) in Noordwijk.

    Menti@Contatto2008 (Grant Agreement)

    First place at regional level for the best ITC project in the sustainable energy field, with a device converting the waste energy of domestic and industrial processes into reusable energy.

    INTERESTS

    Sports(Basketball Football Snowboard Running), Music (to listen and to play), Traveling (just see BEST) and much more;

    PUBLICATIONS

     

    Design Issues and Challenges of File Systems for Flash Memory

    InTech Book Publisher

    EDACs and Test Integration Strategies for NAND Flash memories

    17 - 20 Sep 2010, St. Petersburg, RUSSIA

     

    Exploring Modeling and Testing of NAND Flash memories

    17 - 20 Sep 2010, St. Petersburg, RUSSIA

     

    Automated synthesis of EDACs for FLASH Memories with User- 1Selectable Correction Capability

    11 - 12 Jun 2010

    Anaheim, CA, USA

    FLARE: a Design Environment for Space Applications

    4 - 6 Nov 2009, San Francisco, CA, USA

     

    Flash-memories in Space Applications: Trends and Challenges

    18 - 21 Sep 2009, Moscow, RUSSIA



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