OBJECTIVE:

Provide senior support to Parts Program Management in the selection, acquisition, evaluation, testing, reliability, specification, and application of  Semiconductor Devices and Microcircuits such as field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), microprocessors, peripheral devices, and memories.

EDUCATION:

            Ph.D.   Electrical & Computer Engineering, University of Southern California

            M.S.    Electrical & Computer Engineering, University of Southern California

            B.S.     Electrical & Computer Engineering, University of Tehran

EXPERIENCE:

Joined the Jet Propulsion Laboratory (JPL/NASA) in 2001 as a Senior Member of the Parts Engineering Group of the Electronic Parts Engineering Office. Published more than 60-refereed papers, including a chapter of a text and several manuscripts. Member of  the NASA Electronic Parts and Packaging (NEPP) Program. Task manager on numerous R&D research projectssponsored by JPL,NEPP, and NASA Research and Technology Development (R&TD). Supported all JPL/NASA projects as Senior VLSI specialist.Served as JPL representative to the Government-Industry Data Exchange Program (GIDEP) and JPL ALERT coordinator.  Prepared and coordinated revisions to the JPL Preferred Parts List for Parts Engineering Group. Assisted Parts Acquisition Group in tracking of integrated circuit acquisition for several JPL/NASA projects. 

 Member of the QML Microcircuit Audit team for QML Class Q, V products (DLA aka DSCC)NASA designated Expert on  EEE Parts Engineering on Space Flight Microelectronic Hardware. Team member in the revitalization of Standard Parts Program, helped re-write MIL-PRF-38535 Revision H, reviewer of several SMDs for Monolithic Microcircuits.Member of NASA EEE Parts Assurance Group (NEPAG), a joint partnership of seven NASA Centers and other international Space agencies. Responsibilities include attending weekly level 2 program telecons with the worldwide Space Community for NASA. Representing NASA on DSCC audits of suppliers and mannufacturers, while supporting JPL/NASA flight projects.

 Contributed to practically every mission that JPL as well as other NASA centres have launched in the past several years, as technical task manager and  Senior FPGA/ASIC Specialist. Contributed to several NASA/JPL programs, including Mars Odyssey, Stardust, X-2000, MER, MRO, Cloud Sat, MTO, MSL, OSTM, Aquarius, Dawn, Wise, NuStar, AMT, Kepler, Phoenix, MSL, and Juno. Area of research includes VLSI design automation, FPGA/ASIC design, design for testability and reliability.Membember of a task group assigned to define new Class-Y for non-hermetic Ceramic Flip-Chips for Space applications.

INDUSTRY-RESEARCH

2001-2011       Senior VLSI Specialist, Electronics Parts Engineering Section, JPL/NASA, Pasadena, CA                                .

2006-2011       PI, "Low Power ASIC Design Methodology and Implementation," Northrop    Grumman Corp., Woodland Hills, CA

                                1998-2001       “Reliable and Low Cost Microelectronics for Deep Space”, JPL/NASA

1996-1997       "Fault Tolerant Mission Manager for Autonomous UAVs", Lockheed Martin Skunk Works, Palmdale, CA

1994-1994       NASA/CALTECH Faculty Fellowship, Neural Network and Robotics Section, "VHDL Modeling of ASIC Design  for Testability, Fault Tolerant Digital systems and massively parallel processing", JPL/NASA, Pasadena, CA

1993-1993       NASA/CALTECH Faculty Fellowship , "Behavioral Description of ASIC for Micro-Rover Project", JPL/NASA, Pasadena, CA

ACADEMIC

 1991-Present            Professor, Department of Electrical & Computer Engineering, California State University of Northridge Teaching undergraduate and graduate courses in the area of Computer System & Design Automation, Testing, Fault Tolerant Systems. Research on ASIC/FPGA design and design for testability.

1992-1995           Graduate Coordinator, Department of Electrical & Computer Engineering, California State   University of Northridge

1984-2003       Adjunct Professor, Department of Electrical & Computer Engineering,                                           University of Southern California.

PROFESSIONAL CONTRIBUTIONS

• Member, Board of Directors, San Fernando Valley Engineers' Council 2004-present (the largest Engineer Council in the Nation) .
• Minority Engineering Representative ,the College of Engineering & Computer Science, California State University, Northridge (CSUN)
• Chairman, Symposium on Nanotechnology Conference, Feb. 2008
• Chair,IEEE San Fernando Valley Section, 2000-2004
• Vice Chair, IEEE San FernandoValley Section, 1998-2000
• University Graduate Studies Committee (Presidential Appointee), CSUN

HONORARY MEMBERSHIPS AND AWARDS

• Distinguished Engineering Project Achievement Award, SFV Engineers’ Council, 2010
• NASA Achievement Award, NEPAG (NASA Electronic Parts Assurance Group), 2010
• NASA/JPL Mars Explorer Rover (MER) Group Recognition Award, 2004
• NASA/JPL Mars Explorer Rover (MER) Individual Award, 2004
• IEEE Distinguished Service Award, San Fernando Valley, CA
• The IEEE Third Millennium Medal, for Outstanding Achievement and Contribution
• Engineering Educator of the Year Award, San Fernando Valley Engineers’ Council
• The San Fernando Valley Engineers' Council Merit Award, 1994
• NASA/JPL Faculty Summer Fellowship Awards
• Outstanding Faculty Award, College of Engineering
• Best Professor of the Year Award, Tau Beta Pi Engineering Honor Society, CSUN
• Honorary Member (Eminent Engineer), Tau Beta Pi Engineering Society
• Recipient of several Meritorious Performance and Professional Promise Award (MPPPA), CSUN

PUBLICATIONS

 Published more than 60-refereed papers, including a chapter of a text and several manuscripts. Examples include:

R. Roosta, “FPGA/ASIC for Space Applications,” 14th International Commercialization of Military and Space Electronics Conference and Exhibition (CMSE), Los Angeles, CA, February 8-11, 2010.

 R. Roosta, “Qualification & Screening Issues of Xilinx Virtex-4 FPGAs for Space Applications,” 11^th IEEE Microelectronics Reliability and Qualification Workshop (MRQW), Manhattan Beach, CA, December 8-9, 2009.

 R. Roosta, “FPGA and ASIC Qualification for Space Applications,” 10^th IEEE Microelectronics Reliability and Qualification Workshop (MRQW), Manhattan Beach, CA, December 2-3, 2008.

 R. Roosta et al, "A Dynamic Platform for Reliability Test of Reprogrammable Xilinx FPGAs,”
11th International Commercialization of Military and Space Electronics Conference and Exhibition (CMSE), Los Angeles, CA, March 12-15, 2007.

 R. Roosta,”Xilinx SRAM Based FPGA Testing, Testability, and Reliability Issues,” New Electronic Technologies and Insertion into Flight Programs Workshop NASA/GSF, Greenbelt, MD, January 30- February 1, 2007.

 (Invited Paper) R.Roosta et al, “A Dynamic Platform for Reliability and Environmental Test of Reprogrammable Xilinx Virtex-II 3000 FPGA,”3rd WSEAS/IASME International Conference on Electro Science & Technology for Naval Engineering, Vouliagmeni, Athens, Greece July 11-15, 2006.

 R. Roosta etal "Virtex-II 3000 Dynamic Test Platform with GUI based Software  Automation " 7th International Conference on Military and Aerospace Applicatins (MAPLD),Washington DC, September 8-11, 2004.

 R. Roosta et al "A comparative radiation  study of Actel antifuse -based  and Xilinx SRAM- based FPGAs for Space Applications" ,7th International Conference on Military and Aerospace Applicatins (MAPLD) Washington DC , September 8-11 2004.