- Oct 2014 till Present - Company: European Spallation Source
- Location: Lund, Sweden
- Job Title: FPGA Expert for Fast Beam Interlock.
- Feb 2013 to Sep 2014: Company: University of Dundee / Start Dundee
- Location: Dundee – Scotland.
- Job Title: Spacecraft Engineer.
- Sep 2008 to Aug 2011 - Company: CERN (European Organisation for Nuclear Research).
- Location: Geneva – Switzerland.
- Job Title: Fellow – Beam Instrumentation Designer.
- Feb 2006 to Feb 2007: - Company: CERN (European Organisation for Nuclear Research).
- Location: Geneva – Switzerland.
- Job Title: Technical Student – Optical Link Developer.
- 1997 to 2000: - Company: J&A Ingenieros Informaticos.
- Location: Redovan – Spain.
- Time: 3 years.
- Job Title: Technical service manager
Projects and Researches (see attached document)
- 2014-2016: Fast Beam Interlock: Developing the new ESS Fast interlock system, and unprecedented Interlock for an unprecedented neutron source.
- 2014: Vhissi (Very High Speed Serial Interface): European project and multi-company collaboration to develop a new generation of chips that will set the new standard in Space on-board communications.
- 2013 – 2014: PXIeH card: Design of the new Hardware system platform used by UoD and Star Dundee for the new generation of SpW and SpFi Modules.
- 2013: SpW PnP: Implementation of the updated Standard to speed up network construction (VHDL).
- 2009 – 2011: TRIC: System used to measure and calculate the Beam Intensity on TT2, PSB, LINAC and LEIR.
- 2008 – 2010 : Isolde WD: Upgrade of the old system using the new TRIC Cards (digital integrators)
- 2008: VME RF Multiplexor (8 to 1@3GHz)
- 2007: Optical Link Simulation: Project Developed in CIT based on the simulation of a digital Optical Link (similar to the used on 2006 in CERN). (Mark: 81%).
- 2006: Optical Link: Project Developed in CERN based in an Analogue and Digital Link with VME interface to transmit and control the synchronism signals sent to all the experiments.
- 2005: DVB-S2 - LDPC Coding over AWGN Channel: Project Develop in W.I.T. based in a Emulation write in C++ of this codec over Linux. (Mark: 93%).
- 2003: Design and construction of a Digital Signal processing system for Voice processing: A microcontroller trainer system designed for testing and developing audio algorithms. (Mark: 100%).
- Sep 2004 to June 2007 (Erasmus): Bachelor of Engineering (Honours) in Electronic Engineering - Waterford and Cork Institute of Technology in - Cork - Ireland. (Global Mark: 70%).
Subjects: System Control Theory, Telecommunication Theory, Semiconductor And Materials, English For Erasmus Students, Industrial Studies & Placements, Object Oriented & Windows Programming, Control Engineering, Electronic Engineering, Maths and DSP, Telecommunication Engineering, Computer Engineering, Management, Project, Applied Control System, Real Time Systems, Applied DSP, System Integration, MEMS, Spread Spectrum and Electronic Design, Intenship in CERN
- Sep 1999 to Jun 2003: Bachelor of Engineering in Technical Engineering in Telecommunications: Electronic System - U. of Valencia in Valencia – Spain. (Global mark: 80%).
Subjects: Analogical Components & Electronic Circuits, Digital Components & Electronic Circuits, Linear System Analysis, Mathematical Analysis, Engineering Physic Fundaments, Mathematical Calculations, Introduction Programming, Cad Technical, Synthesis Of Linear Systems, Fundaments Of Computer Architecture, Digital Electronic Systems. , PLC’s, Programming 2, Simulation Technical, Electronics Instrumentation, , Electronics Devices, Introduction To DSP, Fundaments Of Electronics Communication , Microelectronics, Introduction To Telecommunication Systems, Introduction To Control Systems, Projects, Introduction To Commutated Power Source, Technical English For Engineering , Power Electronics Introduction, Information Multimedia Treatment, Data Transmission Nets, Electronic Systems With Microcontrollers, Final Project.
- Jun 1999: Technical Specialist Diploma in Industrial Electronics - Technical institute “Instituto de Formacion Profesional El Palmeral” (Global Mark: 93%).
- Oct 2015
- Type and title: Paper - Overview and design status of the Fast Beam Interlock System at ESS
- Conference ICALEPCS 2015
- ISBN/Link: http://icalepcs.synchrotron.org.au/papers/mopgf138.pdf
- Authors: A. Monera Martinez, R. Andersson, A. Nordt, M. Zaera-Sanz, C Hilbes
- Jan 2014:
- Type and title: Paper - SpaceFibre: Adaptive High-Speed Data-Link for Future Spacecraft Onboard Data Handling
- Conference: 2014 NASA/ESA Conference on Adaptive Hardware and Systems
- ISBN/Link: http://ieeexplore.ieee.org
- Authors: S. Parkes, C. McClements, D. McLaren, A. Monera Martinez, A. Ferrer Florit, A. Gonzalez Villafranca
- Jan 2011:
- Type and title: Article - Upgrade of the CERN PSB/CPS Fast Intensity Measurements
- Conference: 12th International Scientific Conference DIPAC2011
- ISBN/Link: http://adweb.desy.de/mpy/dipac2011/papers/mopd66.pdf
- Authors: A. Monera, M. Andersen, D. Belohrad, L. Jensen, L. Søby, G. Kasprowicz,
- Operative systems: MSDOS 5.0 to 6.3, Windows (ALL including server edition), Linux.
- Office suites: Microsoft Office (all versions). Open Office
- Electronic & CAD Software: Altium, Pspice, Orcad Capture & Layaut, Visual HDL (Allegro v15.5), Quartus(VHDL), Visual Elite(VHDL), Proteus, Matlab, Mplab.
- Programming languages: VHDL, ASM (microchip and Intel), C, C++, Visual Basic, Visual C, TCL/TK.
- Network Management: Medium - Advanced level.
- Computers Hardware: Advanced level.
Language Speaking Reading Writing
- Spanish Mother tongue
- English: Fluent Fluent Fluent
- French Basic Basic Basic
- Motorcycle Riding
- Flying and designing RC airplanes.
- Willing to Learn.
- Willing to Travel & Relocate.
- Full / Clean Driver’s licence.
- Henrik Carling (ESS) Upon request
- Steve Parkes (UoD) firstname.lastname@example.org
- David Belohrad (CERN) David.Belohrad@cern.ch
- Lars Soby (CERN) Soby@cern.ch
- Sophie Baron (CERN) email@example.com
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