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CV: Hardware/Firmware Engineer
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Date Submitted: Last Modified: Current job: Employment Term: Job location: Date available: Industry: KeywordsHEADLINE
Firmware and Hardware Enginner specialiced on design and implementation of digital and analogue hardware. Hardware design from concept through to production including component selection, test, prototype build and debug. Experienced with CAD tools – Altium Designer and OrCAD – for schematic capture, simulation and PCB layout.
Digital design using Hardware Description Language and one or more of: VHDL, Synplify synthesis, Behavioral modeling, RTL modeling. FPGA design using Xilinx and Actel. Digital processing understanding state machine design, multiple clock domains, skew and propagation delay, metastability, synchronous design techniques, fixed and floating point design, pipelining.
Discrete level design of switching and linear circuits using transistors , resistors, capacitors, Op-amps, transimpedance amplifier , instrumentation amplifiers, differential amplifiers, integrators, differentiators, Analog to Digital Converters, Digital to Analog Converters.
Hands on hardware development experience: hardware design tools, power supplies, oscilloscopes, signal generators, frequency counters, soldering stations (thru-hole and SMD).
WORK EXPERIENCE
December 2015 - October 2017
Electronics Spacecraft Engineer
National Institute for Aerospace Technology.
Space Programs and Space Sciences Department.
Payloads and Technique Area
Madrid, Spain
Development, integration and validation of space grade front end electronics (firmware and hardware) for NASA and ESA projects.
March 2015 -August 2015
Electronics Engineer
Erzia Technologies
Santander, Spain
VHDL firmware design: signal processing and radio
frequency control systems for military projects.
April 2013 - January 2015
Electronics Engineer
Paul Scherrer Institut
Laboratory for Particle Physics
Proton Irradiation Facility
Villigen, Switzerland
Characterization and optimization of the Front End Electronics and Central Trigger for POLAR-spaceborne instrument measuring polarization of gamma-ray bursts.Improvement and implementation of test algorithms and parts of firmware for FEE/CT operation and qualification. Qualification and tests of FEE and CT subsystems on laboratory level. Characterization of
POLAR FM model before delivery. Development and implementation of the firmware and software for NGRM and RADEM project.
January 2012- February 2013
Electronics Spacecraft Engineer
National Institute for Aerospace Technology.
Space Programs and Space Sciences Department.
Payloads and Technique Area
Madrid, Spain
Digital and analog electronic design at The Two Towers, a radiation monitor payload (< 5Kg) on board a polar satellite.
VHDL SEL supervision circuits and OBDH designs over two RTSX FPGAs. COTS Digital Signal Controller, from Microchip,
test and validation. Analog and digital electronic design&implementation EM, QM and FM.
March 2011-December 2011
MEIGA Project Trainee
National Institute for Aerospace Technology
Space Programs and Space Sciences Department.
Payloads and Technique Area
Madrid, Spain
Mars Environmental Instrumentation for Ground and Atmosphere. Magnetometer and MetSIS VHDL code programming collaboration,
schematics and layout prototype design&develop for martian sapce applications.
August 2009- July 2010
Research Fellowship. End of Degree Project
Systems Signals and Radiocommunications Department
Visual Telecommunications Application Group
Madrid, Spain
Design and Implementation of a processor for High Definition 3D Stereoscopic Television with a VIRTEX II FPGA.
HD video signal processing with VHDL code. Honors.
October 2007- May 2008
Assistant Scholarship at Electrical Engineering Department
High Technical School of Telecommunication Engineering
Madrid, Spain
Intelligent and Wireless Security Network with Zigbee Devices via ATM commands. Signal processing hardware implementations
and design.
PUBLICATIONS
2012
Instrument Level Design for Radiation Hardness Assurance in The Two Towers monitor. , V. Apéstigue, J. Martinez-Oter,
C. Fernandez, J. Rivas, I. Traseira, J.A. Dominguez, B. Martin, I. Arruego. INTA
RADECS 2012 (Biarritz, France 2012).
The electrical architecture of a complex radiation monitor is presented. It mixes Space-level parts, COTS, and different hardening techniques, to provide high reliability and Radiation Hardness Assurance levels while offering huge performance.
EDUCATION
2002-2010
Polytechnic University of Madrid (Spain)
High Technical School of Telecommunication Engineering
Master Degree , Telecommunication Engineer
Major in Electronics
2012
EUROPLANET-RI NA2 Science Networking
Tallinn, Estonia.
2011
Handbook of Techniques for Radiation Effects Mitigation in ASICs and FPGAs assistant. The European
Space Research and Technology Centre (ESTEC) of ESA.
Noordwijk, The Netherlands
2011
European Conference on Radiation Effects on Components and Systems.
RADECS 2011 Short Course and Technical Sessions.
Seville, Spain
2011
Mars and Society
Summer Course. Complutense University of Madrid
Madrid, Spain
2007
Athens Paris Tech Course: Medical Imaging (TA4)
Université Polytechnique Paris
Paris, France
LANGUAGES
Spanish Mother Language
English Fluent level, written and spoken
OTHER TRAININGS
Skills
VHDL, Verilog, C, C++
I2C, SPI, CAN, RS-422/485/LVDS,UART, SpaceWire, JTAG
Tools
Libero IDE
Synplify
ModelSim
Xilinx ISE
Vivado Design Suite
Pspice
Altium Designer: Capture, Layout
Microchip MP_LAB IDE (dsPIC30F)
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