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  • CV: Head of digital/microelectronics engineering department

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    Personal information
    Contact information
    Candidate Profile
     Date Submitted:14-01-2013
     Last Modified:14-01-2013 (07:03)
    Job information
     Current job:Head of digital/microelectronics engineering department
     Employment Term:Permanent
     Job location:Europe only
     Date available:>3months
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators, , , Launch Systems, Consulting/Engineering Services
     KeywordsDigital design expert from component (ASIC/FPGA) / subsystems (boards) / systems (Electronic Units)

    Personal information






    Date of birth


    19 October 1967


    Place of birth


    La Spezia (SP), ITALY


    Marital status





    Work experience


    Dates (from – to)


    2005 - now

    Name and address of employer



    Type of business or sector


    Avionics products segment, Aerospace products business unit

    Occupation or position held


    Head of FPGA / ASIC R&D / Digital systems department in Space Division

    Main activities and responsibilities


    Development and test, in the position of digital projects and ASIC/FPGA design department head, of many VLSI / boards / unit products that will be released to customers in short and medium time. The main customers are the European Space Agency, the others European space companies (ASTRIUM, Thales Alenia Space, Carlo Gavazzi Space...) and NASA in United States of America, for a range of products from the attitude sensors (star, sun or earth based) to the complexes scientific payloads (micro-gravity, fluid-dynamics, spectrometers) . The main projects covered in this position on the specified time interval are the followings:


    Feasibility study for Lightning Imager (MTG ESA program) with management of specific trade-off between special technology CMOS detectors (with processing electronic inside pixel) and very high speed APS detectors (throughput near to 1Gpixel/sec).


    Development of hyper-spectral payload Main Electronic (PRISMA mission – ASI program). Responsible for this 7-boards main electronics, with massive data rates (from optical head to main electronics 1.5Gbit/sec – from payload to mass memory 600Mbit/sec) and high power to thermal control system and electro-mechanical actuators (150W). Management of external and internal project phases review.


    Digital boards design: management and development of several digital board as support for payloads and attitude sensors. Typical architecture of these boards includes a rad-hard or rad-tolerant CPU (Sparc or DSP), fast front end for Optical head interfacing (Channel link, Spacewire or Wizard link based), processing electronics and system interface (Spacewire or MIL-STD1553) all embedded in a fast, high gate count, rad hard FPGA.


    Development / maintenance / of payload and Attitude Sensor EGSE: Management of GSE systems for internal developments or complete system support. In this frame the typical architecture is based on commercial, custom or off-the-shelf boards, with high-reliability interfaces. Specific knowledge in fault tolerant interfacing, grounding schemes and integration on the final satellite integration site.


    Development for the control logic of a new (APS based) star tracker. This logic integrate these main features:

    • APS (HAS from Cypress) exposure/readout control

    • Pixel flow preprocessing, run length encoding, SEU filtering

    • PROM+EEPROM or double EEPROM boot mode

    • ML16 and DS16 interfaces for TC/TM management

    • Real time digital test interface for virtual stimulation/test

    This ASIC is in the back end phase, and shall be realized with ATMEL in MG2RT technology. The gate count is approx. 290K. The first usage of this ASIC shall be in Alpha Bus program of Thales Alenia Space.


    Development for the MIL-STD1553B remote terminal logic of a new (APS based) star tracker. This ASIC shall overcome some end user restrictions in the MIL-STD1553 integrated circuits produced in USA. The main blocks are the followings:

    • RT1553 macro-cell block

    • Memory management unit for sub-addresses memory efficient usage and FIFO/double bank/depth expansion control

    • CPU support logic: interrupts and event queues management

    • Memory integration for 8Kx16 words

    This ASIC is in the back end phase, and shall be realized with ATMEL in MG2RT technology. The gate count is approx. 330K. The first usage of this ASIC shall be in Alpha Bus program of Thales Alenia Space.


    Re-targeting and partial redesign of an ASIC for earth based attitude sensor. This re-targeting was necessary in order to procure new ASICs for the GALILEO program, because the old supplier (Lockheed Martin Federal System) was no more able to produce circuits in 5V technology. The redesign has been used to remove some end user restrictions integrating a MIL-STD1553 remote terminal interface inside the ASIC. This ASIC has been realized with ATMEL in MG2RTP technology and successfully tested. The gate count is approx. 120K.


    Design of a new CPU board based on AT697E CPU from ATMEL: this board shall substitute (in a couple of years) the actual CPU boards based on AT695 processors for attitude sensors and payloads. This board shall use some FPGA (or ASICs in final product) for interfaces implementation (Spacewire, MIL-STD1553B, CAN bus) and for custom functions implementation (Direct memory access, large data structures elaboration, data co-processors integration).


    Technological developments and test campaign for the usage of last space qualified integrated circuits, like HAS APS (Cypress) sensor characterization, rad hard and rad tolerant FPGA from ATMEL (AT40K and AT280 beta testing), ACTEL and Aeroflex.



    The typical responsibilities for my position in these development are the following:


    • Control for the definition/elaboration/refining of requirements phase

    • Scheduling for the complete development activities

    • Working team constitution, work packages management

    • Project control and progress monitor, phases and project review management

    • Control of subcontractors / integration of their results (AIT functions)

    • Control for final data package and circuit/board/unit release acceptance


    for integrated circuits, board level or complete unit design.


    Dates (from – to)


    2000 - 2004

    Name and address of employer



    Type of business or sector


    Avionics products segment, Aerospace products business unit

    Occupation or position held


    Project/program manager for FPGA / ASIC developments in GA Space Division

    Main activities and responsibilities


    Project manager for a compact PCI board for video camera image acquisition: logic design based on a RTSX ACTEL device, integrating a PCI core and an high speed camera front end. The board has a bus mastering capability in order to directly transfer the image in the CPU memory. This logic integrate also some others blocks:

    • Spacewire interface for image data download

    • UART interface for TC/TM exchange

    • Video camera control (exposure, synchronization)

    This board has been developed in the frame of FASTER project.


    Project manager for the control logic development for PROBA-2 star tracker. This star tracker, based on HAS APS device, is an on-flight demonstrator for the new family of APS based star trackers. The logic, quite similar to the Alpha bus star tracker one, ha been integrated in a RTAX2000S ACTEL space grade – radiation hardened FPGA. This logic has an occupation of about 600K gates.


    Project manager for the control logic of an EQM demonstrator for new generation of APS based star tracker. This star tracker, based on a STAR1000 APS device, was the first APS based approach to the star trackers. The logic, a reduced set of the PROBA-2 one, was implemented on a ALTERA commercial grade device, with a total occupation of about 500K gates. This development was performed in the frame of Bepi Colombo program.


    Project manager for the control logic of an attitude sensor based on the sun position. This logic integrates the following main blocks:

    • STAR1000 APS detector exposure control / readout management

    • SUN search and tracking functions with different rates useful for spinning and non-spinning satellites

    • SEU filtering

    • Pixel flow elaboration, for SUN centroid determination

    • Data interface (ML16/DS16)

    This logic has been integrated in an ATMEL MG2RTP ASIC, with a total gate count of about 150K. This ASIC has been successfully tested and released to the SSS (Smart Sun Sensor) and LCDSS (Low Cost Digital Sun Sensor) programs.


    Project manager for the Vision Based Navigation Camera (VBNC) a compact demonstrator camera for image processing and features extraction in the field of the NPAL (Navigation for Planetary Approach and Landing) ESA project. In this project the developed logic was a system on a chip composed by the following blocks:

    • LEON2 configurable processor, with relevant cache memories

    • STAR1000 APS detector management

    • Memory Management Unit, for image grabbing and fast transfer to the LEON memory

    • Spacewire data interface for image download and TC/TM management

    The complete system was developed in team with ASTRIUM (F) that integrates the terrain features extractor system (FEIC logic) in a separate multi-million gate FPGA. The FPGA for this demonstrator was an ALTERA device from the Stratix family.


    Project manager and program manager for the development of a logic for a star tracker based on CCD TH7890 from ATMEL. This product is a very popular star tracker and the logic has the following blocks:

    • CCD re-programmable exposure and readout sequencer, capable to handle different CCD modes and sequences included the TDI mode for spinning satellites.

    • Pixel preprocessing block for bright stars pre-selection and compression of data via run length encoding.

    • Serial interface capable to manage the star tracker configuration in a single unit or in an optical head / electronic box topology.

    This logic has been developed with a MG2RT ASIC from ATMEL with a gate count of about 350K. This logic is the heart of the star tracker for many ESA, NASA and Italian missions like Herschel-Planck, Messenger, Stereo, MRO, SDO, Pluto, Cosmo and Agile.


    Project manager and program manager for star tracker EGSE. The developed units are for A-STR type and for the new APS based star trackers. The ground support equipments is divided in two sections:

    • TC/TM and power supply manager (AOCS emulator) for sensor development / test and integration in the platform closed loop control.

    • Field of view stimulator for virtual, artificial image elaboration, for performance test and closed loop stability checking.

    Separate EGSE control logic blocks have been developed for SUN and Earth sensors.


    The typical activities for the project manager are the following:


    • Customer and system team work for requirements definition

    • Detailed requirements definition for logic and requirements function mapping

    • Control of the development team

    • Active development of one or more support functions

    • Final integration responsibility




    Dates (from – to)


    1993 - 1999

    Name and address of employer



    Type of business or sector


    Avionics products segment, Aerospace products business unit

    Occupation or position held


    FPGA / ASIC designer in Space Division

    Main activities and responsibilities


    ASIC designer for the control logic of the Star Tracker and Navigation Camera for Rosetta program. The logic integrates a version of a re-programmable CCD controller and the pixel pre-processor. This logic has been integrated in a MG2RT ASIC from ATMEL. The gate count is about 300K.


    ASIC designer for the control logic of a star tracker for SAC-C program. This logic integrates a first version of the re-programmable CCD controller with a single CPU machine: the following versions have two separated CPU for vertical and horizontal scan for more flexibility (MPP modes). This ASIC has been realized with CHIP EXPRESS with a commercial, fast-turnaround, radiation tolerant process.


    ASIC designer for the remapping of IRES ASIC (produced formerly by ABB-HAFO Sweden) in a Lockheed Martin (USA) 0.6um RHCMOS2E technology. The two ASIC (Pitch and Roll counter and Motor scan) have been integrated in single integrated circuit with weight and room saving. This technological remapping was necessary because the ABB-HAFO foundry dismissed the radiation hardened production line. The gate count is about 60K.


    ASIC designer for the control logic of a high reliability camera in the frame of the ESA European Robotic Arm (ERA). This logic integrates the CCD scan and pre-processing functions. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 35K.


    ASIC designer for the control logic of the non autonomous star tracker for XMM mission. The logic integrates the windowed CCD readout and the CPU support functions. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 55K.


    ASIC designer for the control logic of non autonomous star tracker for the Stellar Reference Unit of Cassini (NASA) program. The logic integrates the windowed CCD readout and the pixel pre-elaboration. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 40K.


    ASIC designer for the IRES (Infra-Red earth sensor) project. This attitude earth sensor has two separate logic units, one for the pitch and roll computing from the bolometer (or pyroelectric) detectors scan and the other one for scan mirror control. The two ASICs have been developed with ABB-HAFO (Sweden) with a silicon on sapphire 1.2um process. The gate counts for the two ASICs is approx. 24K and 11K.


    The ASIC/FPGA designer main task are the following:


    • Critical revision of requirements

    • Architectural detailed design

    • Coding and simulations on CAD tools

    • Testing on breadboard for the integrated logic

    • Foundry interface for back end phase


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