Latest Space News
Fri, 20 Sep 2019 15:56:27 +0000
With satellite operators doing a poor job complying with guidelines to deorbit their satellites, incentives or even regulation may be inevitable to address concerns about orbital debris and satellite collisions. SpaceNews.com
Fri, 20 Sep 2019 07:59:18 +0000
The new contract includes support services for the Space Rapid Capabilities Office and the Space Development Agency. SpaceNews.com
Fri, 20 Sep 2019 04:58:15 +0000
Intelsat filed a lawsuit in the New York Supreme Court alleging OneWeb Ltd. and its largest investor SoftBank Group Corp. breached contracts, committed fraud and conspired to steal confidential and proprietary information. SpaceNews.com
Fri, 20 Sep 2019 01:45:46 +0000
A retired NOAA geostationary weather satellite is being handed over to the U.S. Air Force to fill in a gap in the service’s forecasting requirements. SpaceNews.com
Thu, 19 Sep 2019 23:45:01 +0000
As both the number of satellites and the number of potential collisions grow, government and industry officials say they need to improve the ways satellite operators coordinate maneuvers. SpaceNews.com
Thu, 19 Sep 2019 20:50:24 +0000
Countries to consider science payload contributions to respective Luna-26 and Chang’e-7 spacecraft and establish a joint data center for lunar and deep space exploration. SpaceNews.com
Thu, 19 Sep 2019 16:14:05 +0000
Members of a House committee expressed skepticism about NASA’s reliance on commercial launch vehicles to carry out human lunar landings by 2024 rather than an upgraded version of the Space Launch System. SpaceNews.com
Thu, 19 Sep 2019 03:55:14 +0000
It is possible to build improved space traffic management approaches to ensure safe operations in space, a panel of experts in the field said Sept. 18, but it will require more transparency among satellite operators. SpaceNews.com
Thu, 19 Sep 2019 01:14:29 +0000
HawkEye 360 has selected the University of Toronto Institute for Aerospace Studies Space Flight Laboratory to build its next generation of satellites to fly in formation and pinpoint the origin of radio frequency signals. SpaceNews.com
Thu, 19 Sep 2019 00:52:56 +0000
A House version of a stopgap spending bill does not include any special provisions for NASA, which threatens to delay work on lunar landers needed for the agency to achieve its goal of returning astronauts to the moon by 2024. SpaceNews.com
Thu, 19 Sep 2019 00:21:14 +0000
Lt. Gen. John Thompson: “I will categorically state that there is absolutely no bias against the commercial providers in the source selection process." SpaceNews.com
Wed, 18 Sep 2019 23:54:48 +0000
On Sept. 18, 1989, SpaceNews published the first of four monthly preview issues to test the waters for a trade publication focused exclusively on space. Thirty years later, we’re still here covering the business and politics of a greatly expanded global space community. SpaceNews.com
Wed, 18 Sep 2019 21:08:48 +0000
Thompson: A major concern is a misconception that the Space Force will set national space policy. SpaceNews.com
Wed, 18 Sep 2019 19:38:38 +0000
Xenesis, a laser communications startup, plans to conduct a space-based demonstration of its Xen-Hub Optical Communications terminal in 2021 on Bartolomeo, the Airbus Defense and Space external research platform on the International Space Station. SpaceNews.com
Wed, 18 Sep 2019 16:47:04 +0000
ESA needs to succeed with two upcoming parachute tests or will see the ExoMars 2020 landing mission slip to 2022. SpaceNews.com
Wed, 18 Sep 2019 16:40:19 +0000
Inmarsat’s acquisition by Bidco passed a review by the Committee on Foreign Investment in the United States SpaceNews.com
Wed, 18 Sep 2019 12:18:24 +0000
While traditionally we talk about solar flares, anomalies and space debris, increasingly risks in space include cyber risks that have repercussions on the ground. SpaceNews.com
Wed, 18 Sep 2019 12:14:08 +0000
A group of satellite operators and other organizations have banded together to endorse a set of best practices intended to improve space safety, including measures to minimize the risk of collisions in orbit. SpaceNews.com
Wed, 18 Sep 2019 01:26:41 +0000
Raymond: “It’s no longer good enough just to have a satellite that can survive launch and can survive initial operations. You have to have a satellite that is defendable." SpaceNews.com
Tue, 17 Sep 2019 21:03:02 +0000
Boeing is asking the government to force a teaming arrangement with Northrop Grumman for the GBSD program. SpaceNews.com
More space news...
19413 cvs - 626 jobs

LOOKING FOR A JOB?

  • HOME
  • POST YOUR CV
  • JOB SEARCH
  • LOOKING FOR STAFF?

  • HOME
  • REGISTER
  • CV SEARCH
  • POST JOBS
  • CV: Head of digital/microelectronics engineering department

    Printer Friendly

     


    << BACK

    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
     Mobile:<withheld>
    Candidate Profile
     Date Submitted:14-01-2013
     Last Modified:14-01-2013 (07:03)
    Job information
     Current job:Head of digital/microelectronics engineering department
     Employment Term:Permanent
     Job location:Europe only
     Date available:>3months
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators, , , Launch Systems, Consulting/Engineering Services
     KeywordsDigital design expert from component (ASIC/FPGA) / subsystems (boards) / systems (Electronic Units)
    CV

    Personal information

     

    Nationality

     

    ITALIAN


     

    Date of birth

     

    19 October 1967


     

    Place of birth

     

    La Spezia (SP), ITALY

     

    Marital status

     

    Married

     

     

    Work experience

     

    Dates (from – to)

     

    2005 - now

    Name and address of employer

     

    SELEX GALILEO (former GALILEO AVIONICA) (Italy)

    Type of business or sector

     

    Avionics products segment, Aerospace products business unit

    Occupation or position held

     

    Head of FPGA / ASIC R&D / Digital systems department in Space Division

    Main activities and responsibilities

     

    Development and test, in the position of digital projects and ASIC/FPGA design department head, of many VLSI / boards / unit products that will be released to customers in short and medium time. The main customers are the European Space Agency, the others European space companies (ASTRIUM, Thales Alenia Space, Carlo Gavazzi Space...) and NASA in United States of America, for a range of products from the attitude sensors (star, sun or earth based) to the complexes scientific payloads (micro-gravity, fluid-dynamics, spectrometers) . The main projects covered in this position on the specified time interval are the followings:


     

    Feasibility study for Lightning Imager (MTG ESA program) with management of specific trade-off between special technology CMOS detectors (with processing electronic inside pixel) and very high speed APS detectors (throughput near to 1Gpixel/sec).


     

    Development of hyper-spectral payload Main Electronic (PRISMA mission – ASI program). Responsible for this 7-boards main electronics, with massive data rates (from optical head to main electronics 1.5Gbit/sec – from payload to mass memory 600Mbit/sec) and high power to thermal control system and electro-mechanical actuators (150W). Management of external and internal project phases review.


     

    Digital boards design: management and development of several digital board as support for payloads and attitude sensors. Typical architecture of these boards includes a rad-hard or rad-tolerant CPU (Sparc or DSP), fast front end for Optical head interfacing (Channel link, Spacewire or Wizard link based), processing electronics and system interface (Spacewire or MIL-STD1553) all embedded in a fast, high gate count, rad hard FPGA.


     

    Development / maintenance / of payload and Attitude Sensor EGSE: Management of GSE systems for internal developments or complete system support. In this frame the typical architecture is based on commercial, custom or off-the-shelf boards, with high-reliability interfaces. Specific knowledge in fault tolerant interfacing, grounding schemes and integration on the final satellite integration site.


     

    Development for the control logic of a new (APS based) star tracker. This logic integrate these main features:

    • APS (HAS from Cypress) exposure/readout control

    • Pixel flow preprocessing, run length encoding, SEU filtering

    • PROM+EEPROM or double EEPROM boot mode

    • ML16 and DS16 interfaces for TC/TM management

    • Real time digital test interface for virtual stimulation/test

    This ASIC is in the back end phase, and shall be realized with ATMEL in MG2RT technology. The gate count is approx. 290K. The first usage of this ASIC shall be in Alpha Bus program of Thales Alenia Space.


     

    Development for the MIL-STD1553B remote terminal logic of a new (APS based) star tracker. This ASIC shall overcome some end user restrictions in the MIL-STD1553 integrated circuits produced in USA. The main blocks are the followings:

    • RT1553 macro-cell block

    • Memory management unit for sub-addresses memory efficient usage and FIFO/double bank/depth expansion control

    • CPU support logic: interrupts and event queues management

    • Memory integration for 8Kx16 words

    This ASIC is in the back end phase, and shall be realized with ATMEL in MG2RT technology. The gate count is approx. 330K. The first usage of this ASIC shall be in Alpha Bus program of Thales Alenia Space.


     

    Re-targeting and partial redesign of an ASIC for earth based attitude sensor. This re-targeting was necessary in order to procure new ASICs for the GALILEO program, because the old supplier (Lockheed Martin Federal System) was no more able to produce circuits in 5V technology. The redesign has been used to remove some end user restrictions integrating a MIL-STD1553 remote terminal interface inside the ASIC. This ASIC has been realized with ATMEL in MG2RTP technology and successfully tested. The gate count is approx. 120K.


     

    Design of a new CPU board based on AT697E CPU from ATMEL: this board shall substitute (in a couple of years) the actual CPU boards based on AT695 processors for attitude sensors and payloads. This board shall use some FPGA (or ASICs in final product) for interfaces implementation (Spacewire, MIL-STD1553B, CAN bus) and for custom functions implementation (Direct memory access, large data structures elaboration, data co-processors integration).


     

    Technological developments and test campaign for the usage of last space qualified integrated circuits, like HAS APS (Cypress) sensor characterization, rad hard and rad tolerant FPGA from ATMEL (AT40K and AT280 beta testing), ACTEL and Aeroflex.


     


     

    The typical responsibilities for my position in these development are the following:


     

    • Control for the definition/elaboration/refining of requirements phase

    • Scheduling for the complete development activities

    • Working team constitution, work packages management

    • Project control and progress monitor, phases and project review management

    • Control of subcontractors / integration of their results (AIT functions)

    • Control for final data package and circuit/board/unit release acceptance

       

    for integrated circuits, board level or complete unit design.

     

    Dates (from – to)

     

    2000 - 2004

    Name and address of employer

     

    GALILEO AVIONICA (formerly OFFICINE GALILEO) (Italy)

    Type of business or sector

     

    Avionics products segment, Aerospace products business unit

    Occupation or position held

     

    Project/program manager for FPGA / ASIC developments in GA Space Division

    Main activities and responsibilities

     

    Project manager for a compact PCI board for video camera image acquisition: logic design based on a RTSX ACTEL device, integrating a PCI core and an high speed camera front end. The board has a bus mastering capability in order to directly transfer the image in the CPU memory. This logic integrate also some others blocks:

    • Spacewire interface for image data download

    • UART interface for TC/TM exchange

    • Video camera control (exposure, synchronization)

    This board has been developed in the frame of FASTER project.


     

    Project manager for the control logic development for PROBA-2 star tracker. This star tracker, based on HAS APS device, is an on-flight demonstrator for the new family of APS based star trackers. The logic, quite similar to the Alpha bus star tracker one, ha been integrated in a RTAX2000S ACTEL space grade – radiation hardened FPGA. This logic has an occupation of about 600K gates.


     

    Project manager for the control logic of an EQM demonstrator for new generation of APS based star tracker. This star tracker, based on a STAR1000 APS device, was the first APS based approach to the star trackers. The logic, a reduced set of the PROBA-2 one, was implemented on a ALTERA commercial grade device, with a total occupation of about 500K gates. This development was performed in the frame of Bepi Colombo program.


     

    Project manager for the control logic of an attitude sensor based on the sun position. This logic integrates the following main blocks:

    • STAR1000 APS detector exposure control / readout management

    • SUN search and tracking functions with different rates useful for spinning and non-spinning satellites

    • SEU filtering

    • Pixel flow elaboration, for SUN centroid determination

    • Data interface (ML16/DS16)

    This logic has been integrated in an ATMEL MG2RTP ASIC, with a total gate count of about 150K. This ASIC has been successfully tested and released to the SSS (Smart Sun Sensor) and LCDSS (Low Cost Digital Sun Sensor) programs.


     

    Project manager for the Vision Based Navigation Camera (VBNC) a compact demonstrator camera for image processing and features extraction in the field of the NPAL (Navigation for Planetary Approach and Landing) ESA project. In this project the developed logic was a system on a chip composed by the following blocks:

    • LEON2 configurable processor, with relevant cache memories

    • STAR1000 APS detector management

    • Memory Management Unit, for image grabbing and fast transfer to the LEON memory

    • Spacewire data interface for image download and TC/TM management

    The complete system was developed in team with ASTRIUM (F) that integrates the terrain features extractor system (FEIC logic) in a separate multi-million gate FPGA. The FPGA for this demonstrator was an ALTERA device from the Stratix family.


     

    Project manager and program manager for the development of a logic for a star tracker based on CCD TH7890 from ATMEL. This product is a very popular star tracker and the logic has the following blocks:

    • CCD re-programmable exposure and readout sequencer, capable to handle different CCD modes and sequences included the TDI mode for spinning satellites.

    • Pixel preprocessing block for bright stars pre-selection and compression of data via run length encoding.

    • Serial interface capable to manage the star tracker configuration in a single unit or in an optical head / electronic box topology.

    This logic has been developed with a MG2RT ASIC from ATMEL with a gate count of about 350K. This logic is the heart of the star tracker for many ESA, NASA and Italian missions like Herschel-Planck, Messenger, Stereo, MRO, SDO, Pluto, Cosmo and Agile.


     

    Project manager and program manager for star tracker EGSE. The developed units are for A-STR type and for the new APS based star trackers. The ground support equipments is divided in two sections:

    • TC/TM and power supply manager (AOCS emulator) for sensor development / test and integration in the platform closed loop control.

    • Field of view stimulator for virtual, artificial image elaboration, for performance test and closed loop stability checking.

    Separate EGSE control logic blocks have been developed for SUN and Earth sensors.


     

    The typical activities for the project manager are the following:


     

    • Customer and system team work for requirements definition

    • Detailed requirements definition for logic and requirements function mapping

    • Control of the development team

    • Active development of one or more support functions

    • Final integration responsibility

     

     

     

    Dates (from – to)

     

    1993 - 1999

    Name and address of employer

     

    OFFICINE GALILEO (Italy)

    Type of business or sector

     

    Avionics products segment, Aerospace products business unit

    Occupation or position held

     

    FPGA / ASIC designer in Space Division

    Main activities and responsibilities

     

    ASIC designer for the control logic of the Star Tracker and Navigation Camera for Rosetta program. The logic integrates a version of a re-programmable CCD controller and the pixel pre-processor. This logic has been integrated in a MG2RT ASIC from ATMEL. The gate count is about 300K.


     

    ASIC designer for the control logic of a star tracker for SAC-C program. This logic integrates a first version of the re-programmable CCD controller with a single CPU machine: the following versions have two separated CPU for vertical and horizontal scan for more flexibility (MPP modes). This ASIC has been realized with CHIP EXPRESS with a commercial, fast-turnaround, radiation tolerant process.


     

    ASIC designer for the remapping of IRES ASIC (produced formerly by ABB-HAFO Sweden) in a Lockheed Martin (USA) 0.6um RHCMOS2E technology. The two ASIC (Pitch and Roll counter and Motor scan) have been integrated in single integrated circuit with weight and room saving. This technological remapping was necessary because the ABB-HAFO foundry dismissed the radiation hardened production line. The gate count is about 60K.


     

    ASIC designer for the control logic of a high reliability camera in the frame of the ESA European Robotic Arm (ERA). This logic integrates the CCD scan and pre-processing functions. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 35K.


     

    ASIC designer for the control logic of the non autonomous star tracker for XMM mission. The logic integrates the windowed CCD readout and the CPU support functions. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 55K.


     

    ASIC designer for the control logic of non autonomous star tracker for the Stellar Reference Unit of Cassini (NASA) program. The logic integrates the windowed CCD readout and the pixel pre-elaboration. This ASIC has been built using the Lockheed Martin Federal System (USA) 0.6um RHCMOS2E technology, with a gate count of about 40K.


     

    ASIC designer for the IRES (Infra-Red earth sensor) project. This attitude earth sensor has two separate logic units, one for the pitch and roll computing from the bolometer (or pyroelectric) detectors scan and the other one for scan mirror control. The two ASICs have been developed with ABB-HAFO (Sweden) with a silicon on sapphire 1.2um process. The gate counts for the two ASICs is approx. 24K and 11K.


     

    The ASIC/FPGA designer main task are the following:


     

    • Critical revision of requirements

    • Architectural detailed design

    • Coding and simulations on CAD tools

    • Testing on breadboard for the integrated logic

    • Foundry interface for back end phase

     


    Registering is the only way of posting vacancies and obtaining contact details of candidates in our CV database.

    All it takes is a few minutes and a credit card (Visa or American Express). To sign-up to this service, simply click on the Register link and fill in the form. You will then have instant access to our system after on-line payment where you will be able to complete the transaction in either US Dollars, UK Pounds or Euros.

    All online credit/debit card transitions are handled through our secure third party payment processors at WorldPay. Worldpay are part of The Royal Bank of Scotland Group, the 5th biggest banking group in the world, WorldPay payment solutions are trusted by thousands of businesses, big and small worldwide. 

    Pricing starts at €450 (approx £400 or US$500 - use the convert tool for an exact conversion) for one month unlimited job postings and unlimited CV database access (for one user), with package discounts available if you have more permanent recruiting needs. For example, a Gold subscription will give you unlimited jobs posting and unlimited CV database access for one year at just over €250 per month!

     

    2019 Pricing Structure (excluding VAT):

    1 month - Discovery 450 euros convert
    3 months - Bronze 1150 euros convert
    6 months - Silver 1950 euros convert
    12 months - Gold 3200 euros convert

     

    If online payment is not convenient, give us a call at +33(0)622757477 or send us an email at sales@space-careers.com. We will set up an account for you and invoice you. Note that you can also pay through PayPal.

     

    Subscriptions

     

    Please note that the posting of academic positions is free of charge. All you need to do is email us your job description and we will post it for you.

     

    VAT:

    Spacelinks is based in France so the following European Union regulations regarding electronic commerce apply:
    - if your business is located outside the EU, VAT does not apply to you
    - if your business is located in France, you will be charged a 20% VAT
    - if your business is located in the EU and you don't have a valid VAT registration number, you will be charged a 20% VAT
    - if your business is located in the EU and you do have a valid VAT registration number, you won't be charged VAT provided you give us your VAT number (mandatory for invoicing)

     

    Support:

    For sales enquiries and general information, you can call us on +33(0)622757477.
    Support is available Mon-Fri on +33(0)622757477 or via email. Out-of-hours support is provided only via email.

    Please also note that we are located in France. Our normal office hours are 09:00 to 18:00 Monday to Friday. France timezone is GMT+1.

     

    Warning:

    We are very serious about our job seekers privacy so only legitimate recruiters and employers are eligible for a recruiter account. All subscriptions requests will be manually approved and recruiter accounts constantly monitored. Users who enter inaccurate or incomplete information will not gain access to post jobs or search resumes. Sharing of login details with a third party will result in the suspension of the recruiter's account with no subscription refund.
    Recruitment agencies are only eligible for a Gold package and recruitment agencies recruiting for companies already using Space Careers will not be accepted.

    To ensure you are approved, please include the following on your application:
    * The website address of your Company. Under construction websites will be rejected.
    * Email - Must end in @yourcompany.com. Applications using free email accounts such as Hotmail, Yahoo or Gmail will be rejected.

    Individual exceptions can be made on a case by case basis by emailing sales@space-careers.com. Accounts found not to be in compliance will be deleted.

     
    Terms & ConditionsCopyright ©2019 Spacelinks
    Web Analytics