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Wed, 14 Nov 2018 01:36:05 +0000
Griffin said nothing has yet been decided on how the Space Development Agency should be organized. SpaceNews.com
Tue, 13 Nov 2018 23:50:40 +0000
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Tue, 13 Nov 2018 18:27:05 +0000
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Tue, 13 Nov 2018 12:20:10 +0000
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Tue, 13 Nov 2018 08:34:23 +0000
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Mon, 12 Nov 2018 11:33:48 +0000
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Sun, 11 Nov 2018 04:53:41 +0000
Rocket Lab successfully launched its Electron rocket Nov. 10 on a long-delayed first commercial mission for the small launch vehicle. SpaceNews.com
Sat, 10 Nov 2018 04:21:24 +0000
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Sat, 10 Nov 2018 01:02:53 +0000
The Trump administration’s desire to establish a Space Force could be in jeopardy next year after Democrats assume control of the House, while the departure of a key House appropriator could spell trouble for NASA missions to the potentially habitable moon of Europa. SpaceNews.com
Fri, 09 Nov 2018 11:49:52 +0000
NASA has certified SpaceX’s Falcon 9 to launch the agency’s most important science missions, giving the agency new options that could result in lower costs. SpaceNews.com
Thu, 08 Nov 2018 19:00:37 +0000
Building and launching spacecraft sometimes gets so much attention that the ground segment — user terminals, command and control systems and network operations —isn’t always ready even after a satellite is in space. SpaceNews.com
Thu, 08 Nov 2018 16:23:49 +0000
Ryals suggested a Space Development Agency could be helpful in providing a single voice for military space requirements. SpaceNews.com
Thu, 08 Nov 2018 14:03:49 +0000
The Canadian military, already a partner on two U.S. military satellite communications systems, is in discussions to use a third constellation that was until recently a U.S.-only system. SpaceNews.com
Thu, 08 Nov 2018 14:02:55 +0000
Grason: “We’re seeing a different type of support to get after the transformation, to elevate commercial satcom to where it needs to be, as vital infrastructure." SpaceNews.com
Thu, 08 Nov 2018 01:09:00 +0000
SpaceX Chief Executive Elon Musk said Nov. 7 that his company will attempt an orbital flight of a reusable version of a Falcon 9 upper stage by the middle of next year to test technologies for the company’s next-generation launch vehicle. SpaceNews.com
Wed, 07 Nov 2018 21:45:28 +0000
After completing the purchase of Sea Launch in April, S7 Group now views expendable rockets as uncompetitive. SpaceNews.com
Wed, 07 Nov 2018 17:09:05 +0000
DARPA has identified eight sites in the United States that it plans to use for a commercial launch competition, a selection that addresses one of the major concerns of potential competitors. SpaceNews.com
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  • CV: Sr. ASIC/DSP Design Engineer, Technical Lead

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    Personal information
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    Candidate Profile
     Date Submitted:24-07-2013
     Last Modified:24-07-2013 (12:10)
    Job information
     Current job:Sr. ASIC/DSP Design Engineer, Technical Lead
     Employment Term:Permanent
     Job location:Own country
     Date available:within 2 months
     Industry:
     Keywords
    CV

     PROFESSIONAL PROFILE

    Highly motivated professional with more than 15 years of hardware engineering experience in telecom, semiconductor, aerospace and test&measurement industry.

    Executed projects range from mixed-signal ASIC design, FPGA design of real-time spectrum analysis and frequency mask triggering systems, ASIC and FPGA design of high-end GPS/Galileo/Glonass baseband receivers, ASIC prototyping by means of FPGAs for several ASICs used in Voice over IP applications, board and FPGA design for high volume, low cost modems and high-speed board design for high-end ATM based switching systems. Proven track record of successfully taking designs from architecture phase up to manufacturing release.

    Flexible and versatile engineer with excellent team building skills and talent for quickly mastering new technologies. Eager to learn. Self starter who can work with minimal supervision. 

    SKILLS

    • Matlab/Simulink /System Generator/C++ modeling of DSP algorithms and systems.
    • ASIC/FPGA specification, architecture, design and simulation in Verilog/VHDL.
    • ASIC prototyping and verification.
    • RTL Synthesis + Simulation + Static Timing Analysis: Synplify Pro and Certify (Synplicity), Modelsim (Mentor Graphics), Design Compiler, Prime Time (Synopsys).
    • Place and Route: Xilinx, Altera.
    • Board design (component selection, schematic entry, signal integrity, coordination of PCB layout, EMI/EMC, ESD, safety, test, follow-up manufacturing).
    • Pre and post layout signal integrity simulations by means of IBIS models.
    • Testing and debugging (oscilloscope, logic analyzer, pattern generator, BERT, …).

    PROFESSIONAL BACKGROUND

    Confidential (Belgium)   (Mar 2007 – Present)

    Sr. ASIC/DSP Design Engineer, Technical Lead

    As technical lead of a team working on a breakthrough high-performance A/D converter ASIC, responsible for:

    • Complete development cycle of the digital part (specification, design and modeling of digital corrections for analog impairments, bit true and cycle accurate C++ simulations, verification test plan and follow-up, prototyping on Xilinx platform, validation of silicon in system context).
    • Coordination of the technical design aspects and maintaining daily communication with the team in California that worked on the analog part of the ASIC.
    • Coaching of other team members and follow-up on contractors (VHDL coding, synthesis, verification).

    The tape-out was a big success and the ASIC is now a key component in Agilent's future spectrum analyzers. Promoted to Expert.

    The validation platform of the A/D converter was re-used to develop a complete real-time spectrum analysis and frequency mask triggering system for detecting and capturing transient signals with high probability of intercept. This involved:

    • Investigating customer requirements and defining an architecture which enables significant differentiation from competitors on the long term.
    • Specification, modeling in Simulink/System Generator, micro-architecture, design, simulation and testing.

    Part of the work was reported about in the European FP7 projects Samurai and Qosmos and were rated excellent at the review.

     

    Septentrio Satellite Navigation (Leuven, Belgium)   (Feb 2004 – Feb 2007)

    ASIC/FPGA Design Engineer

    Responsible for specification and design of a new architecture for a high-end, multi-frequency GNSS receiver ASIC.

    • Designed and simulated in VHDL multiple blocks (digital front-end with FIR filters, P/Y channel with adaptive semi-codeless controller, fast acquisition unit based on matched filter and FFT, …).
    • Prototyped a reduced channel GPS receiver in Xilinx Virtex II Pro (XC2VP40) and Virtex4 (XC4VLX40).
    • Integrated Xilinx’s MicroBlaze embedded processor with its peripherals (UART, interrupt controler,…) for test purposes and wrote C code for test applications for the embedded processor.

    The ASIC was first time right and is since then the core component of the AsteRx products.

    Responsible for the design of a new compact, low power architecture for a single frequency GPS/Galileo receiver targeted for lower cost in Xilinx Spartan3 (XC3S1000).

     

    Contracting and college (University of California Santa Cruz Extension)   (Sep 2002 –  Jan 2004)

    GlobespanVirata / iCompression (Santa Clara, California)  (Jan 2001 – Aug 2002)

    Hardware Engineer

    Responsible for ASIC prototyping for several ASICs used in VoIP applications.

    • Partitioned large complex designs among multiple FPGAs (one board had 8 Xilinx Virtex-II XC2V6000) and wrote Verilog code to support the integration and partitioning.
    • Performed synthesis, place and route, floorplanning and static timing analysis.
    • Debugged the ASIC code mapped in multiple FPGAs, in the lab with logic analyzer and oscilloscope.

    The prototyping allowed the ASIC designers to find problems in the chip, not encountered earlier during simulation, and saved over $500k for each tape-out iteration. Also, it created a platform for the DSP group to debug their software before the ASIC was available.

     

    Datax (Antwerp, Belgium)   (Jan 2000 – Dec 2000)

    Hardware Development Engineer

    Responsible for the entire development of the 2MCNV product, which provides an interface conversion between E1/T1 and X21, V35 or Ethernet.  This included:

    • Writing user requirements specification.
    • Feasibility study (board functionality, variants, physical constraints), power budget and cost analysis.
    • Evaluation of all required components and integrated circuits (analog and digital).
    • Design and simulation in VHDL (interface conversion, test loop handling,…), implemented in Altera’s MAX3000 series to achieve low cost at high volume.
    • Schematic capture, coordination of board layout and mechanical design.
    • Debug and test prototypes (EMI/EMC, ESD and compliancy tests), follow-up manufacturing.

     

    Alcatel (Antwerp, Belgium)   (Aug 1996 - Dec 1999)

    Hardware Design Engineer                                                                                                                                                   

    Designed high-speed ABCE board, which converts traffic from the broadband switch into ATM cells and extracts CBR traffic (composed of multiple E0, E1 connections), which is packed in a format suitable for narrow band. This included:

    • Feasibility study (board functionality, thermal behavior, floorplanning).
    • Writing design specification.
    • Schematic capture and follow-up board layout process.
    • Responsible for in-depth analysis of signal integrity by means of simulations and modeling (IBIS).
    • Debug and test prototypes.

    Participated in the architecture phase (feasibility study, processor evaluation,…) of high-speed ALK board, which terminates ATM cells and converts traffic towards the broadband switch. 

     

    Telkon (Antwerp, Belgium)   (Aug 1995 – Jun 1996)

    Internship + Final Thesis

    Developed and simulated a 16 QAM modem. This included the design of multiple digital filters using Matlab, and the development and implementation of several algorithms in C/C++.

     

    EDUCATIONAL BACKGROUND
     

    VLSI design engineering,University of California Santa Cruz Extension, USA. (2002-2003)

    Postgraduate degree in Telecommunications, IMEC Belgium (1997-1999)

    M.S. in Electrical Engineering, KIHO Belgium (1993-1996)

     

    Additional Training:

    Signal Processing with Simulink, Cambridge  (Dec 2011)               

    Comprehensive C++ (Doulos)  (Mar 2008)

    GPS Operation for Engineers & Technical Professionals (course 356)  (May 2005)

    EMC/EMI, TU Delft (Nov 1997)

     

    LANGUAGES

    Dutch: Mother tongue

    English: Excellent knowledge

    German: Intermediate knowledge

    French: Basic knowledge

     

    References:

    Available upon request.


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