Highly motivated professional with more than 15 years of hardware engineering experience in telecom, semiconductor, aerospace and test&measurement industry.
Executed projects range from mixed-signal ASIC design, FPGA design of real-time spectrum analysis and frequency mask triggering systems, ASIC and FPGA design of high-end GPS/Galileo/Glonass baseband receivers, ASIC prototyping by means of FPGAs for several ASICs used in Voice over IP applications, board and FPGA design for high volume, low cost modems and high-speed board design for high-end ATM based switching systems. Proven track record of successfully taking designs from architecture phase up to manufacturing release.
Flexible and versatile engineer with excellent team building skills and talent for quickly mastering new technologies. Eager to learn. Self starter who can work with minimal supervision.
Confidential (Belgium) (Mar 2007 – Present)
Sr. ASIC/DSP Design Engineer, Technical Lead
As technical lead of a team working on a breakthrough high-performance A/D converter ASIC, responsible for:
The tape-out was a big success and the ASIC is now a key component in Agilent's future spectrum analyzers. Promoted to Expert.
The validation platform of the A/D converter was re-used to develop a complete real-time spectrum analysis and frequency mask triggering system for detecting and capturing transient signals with high probability of intercept. This involved:
Part of the work was reported about in the European FP7 projects Samurai and Qosmos and were rated excellent at the review.
Septentrio Satellite Navigation (Leuven, Belgium) (Feb 2004 – Feb 2007)
ASIC/FPGA Design Engineer
Responsible for specification and design of a new architecture for a high-end, multi-frequency GNSS receiver ASIC.
The ASIC was first time right and is since then the core component of the AsteRx products.
Responsible for the design of a new compact, low power architecture for a single frequency GPS/Galileo receiver targeted for lower cost in Xilinx Spartan3 (XC3S1000).
Contracting and college (University of California Santa Cruz Extension) (Sep 2002 – Jan 2004)
GlobespanVirata / iCompression (Santa Clara, California) (Jan 2001 – Aug 2002)
Responsible for ASIC prototyping for several ASICs used in VoIP applications.
The prototyping allowed the ASIC designers to find problems in the chip, not encountered earlier during simulation, and saved over $500k for each tape-out iteration. Also, it created a platform for the DSP group to debug their software before the ASIC was available.
Datax (Antwerp, Belgium) (Jan 2000 – Dec 2000)
Hardware Development Engineer
Responsible for the entire development of the 2MCNV product, which provides an interface conversion between E1/T1 and X21, V35 or Ethernet. This included:
Alcatel (Antwerp, Belgium) (Aug 1996 - Dec 1999)
Hardware Design Engineer
Designed high-speed ABCE board, which converts traffic from the broadband switch into ATM cells and extracts CBR traffic (composed of multiple E0, E1 connections), which is packed in a format suitable for narrow band. This included:
Participated in the architecture phase (feasibility study, processor evaluation,…) of high-speed ALK board, which terminates ATM cells and converts traffic towards the broadband switch.
Telkon (Antwerp, Belgium) (Aug 1995 – Jun 1996)
Internship + Final Thesis
Developed and simulated a 16 QAM modem. This included the design of multiple digital filters using Matlab, and the development and implementation of several algorithms in C/C++.
VLSI design engineering,University of California Santa Cruz Extension, USA. (2002-2003)
Postgraduate degree in Telecommunications, IMEC Belgium (1997-1999)
M.S. in Electrical Engineering, KIHO Belgium (1993-1996)
Signal Processing with Simulink, Cambridge (Dec 2011)
Comprehensive C++ (Doulos) (Mar 2008)
GPS Operation for Engineers & Technical Professionals (course 356) (May 2005)
EMC/EMI, TU Delft (Nov 1997)
Dutch: Mother tongue
English: Excellent knowledge
German: Intermediate knowledge
French: Basic knowledge
Available upon request.
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