Latest Space News
Fri, 18 May 2018 20:18:02 +0000
As NASA formally requests proposals for studies on the commercialization of low Earth orbit, another study presented at a congressional hearing May 17 concludes commercial space stations are unlikely to be financially viable in the mid-2020s. SpaceNews.com
Fri, 18 May 2018 14:48:14 +0000
Members of a NASA safety panel said May 17 they believed that a SpaceX approach for fueling its Falcon 9 rockets known as “load-and-go” could be used for future commercial crew missions. SpaceNews.com
Fri, 18 May 2018 03:02:18 +0000
As House appropriators approved a spending bill May 17 that partially restores funding for a NASA astrophysics mission slated for cancellation, the agency’s administrator said he was “90 percent” confident that the mission will continue. SpaceNews.com
Thu, 17 May 2018 23:25:08 +0000
Planet hopes to grab market share by offering “guaranteed collection” twice a day. SpaceNews.com
Thu, 17 May 2018 22:42:51 +0000
NASA is dealing with a contamination problem with tubing in part of the core stage of the first Space Launch System vehicle, an issue that could contribute to further delays for its launch. SpaceNews.com
Thu, 17 May 2018 20:27:37 +0000
Nine satellite companies agreed May 17 to donate satellite capacity and equipment to the United Nations, seeking to coordinate their responses to natural disasters. SpaceNews.com
Thu, 17 May 2018 19:45:38 +0000
Nearly 600 members of a union that has been on strike against United Launch Alliance for almost two weeks will vote on a new contract May 19 that would end the labor dispute. SpaceNews.com
Thu, 17 May 2018 17:10:18 +0000
SpaceX and OneWeb, two companies building thousands of satellites for broadband services, both expect to connect billions of the world's least-served to the internet. The two most prominent developers of electronically steered antennas don’t share that aspiration, however. SpaceNews.com
Thu, 17 May 2018 15:43:28 +0000
The new Pentagon-based vice commander of Air Force Space Command, Lt. Gen. David “DT” Thompson, made his first public appearance May 15, 2018, at a Washington Space Business Roundtable luncheon. SpaceNews.com
Thu, 17 May 2018 09:34:13 +0000
Testimony by NASA’s Inspector General at a May 16 hearing provided new support to efforts by two senators to block plans to end funding of the International Space Station in 2025. SpaceNews.com
Wed, 16 May 2018 22:33:57 +0000
A spending bill to be marked up by the House Appropriations Committee would provide some funding for a NASA space telescope proposed for cancellation, but not necessarily enough to keep the mission on schedule. SpaceNews.com
Wed, 16 May 2018 22:13:26 +0000
A British billionaire has invested in a company operating a ground station that has aspirations to support commercial missions beyond Earth orbit. SpaceNews.com
Wed, 16 May 2018 21:52:44 +0000
Todd Harrison, CSIS senior fellow: “With hosted payloads, there are a lot of great opportunities to increase resiliency and capacity.” SpaceNews.com
Wed, 16 May 2018 18:38:50 +0000
Aireon raised $69 million from a British partner, enabling the aircraft-tracking startup to begin making hosting payments to Iridium Communications. SpaceNews.com
Wed, 16 May 2018 02:14:44 +0000
Inflight connectivity provider Global Eagle will help Telesat in design and test the operator’s low Earth orbit satellite constellation, the companies announced May 15. SpaceNews.com
Tue, 15 May 2018 20:26:23 +0000
A NASA advisory committee, concerned about delays in the development of commercial crew systems, wants the agency to look at options where the International Space Station is operated with a reduced crew. SpaceNews.com
Tue, 15 May 2018 19:52:12 +0000
Thompson: “We needed somebody to work space every single day. Before, I didn’t recognize how much that was needed." SpaceNews.com
Tue, 15 May 2018 19:37:15 +0000
Eutelsat on May 14 said it is taking steps to secure a foothold in the European broadband market after last month’s decision to forgo jointly funding a satellite with Viasat turned the two companies into direct competitors. SpaceNews.com
Tue, 15 May 2018 18:11:00 +0000
It is still early days for this emerging sector, but 2018 will be the year that Chinese commercial launch companies begin to take off. SpaceNews.com
Tue, 15 May 2018 17:11:02 +0000
The modern ship is always in touch. It navigates by GPS, just as you do. Satellites carry email, voice calls, weather forecasts and navigation charts. SpaceNews.com
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  • CV: Sr. ASIC/DSP Design Engineer, Technical Lead

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    Personal information
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    Candidate Profile
     Date Submitted:24-07-2013
     Last Modified:24-07-2013 (12:10)
    Job information
     Current job:Sr. ASIC/DSP Design Engineer, Technical Lead
     Employment Term:Permanent
     Job location:Own country
     Date available:within 2 months
     Industry:
     Keywords
    CV

     PROFESSIONAL PROFILE

    Highly motivated professional with more than 15 years of hardware engineering experience in telecom, semiconductor, aerospace and test&measurement industry.

    Executed projects range from mixed-signal ASIC design, FPGA design of real-time spectrum analysis and frequency mask triggering systems, ASIC and FPGA design of high-end GPS/Galileo/Glonass baseband receivers, ASIC prototyping by means of FPGAs for several ASICs used in Voice over IP applications, board and FPGA design for high volume, low cost modems and high-speed board design for high-end ATM based switching systems. Proven track record of successfully taking designs from architecture phase up to manufacturing release.

    Flexible and versatile engineer with excellent team building skills and talent for quickly mastering new technologies. Eager to learn. Self starter who can work with minimal supervision. 

    SKILLS

    • Matlab/Simulink /System Generator/C++ modeling of DSP algorithms and systems.
    • ASIC/FPGA specification, architecture, design and simulation in Verilog/VHDL.
    • ASIC prototyping and verification.
    • RTL Synthesis + Simulation + Static Timing Analysis: Synplify Pro and Certify (Synplicity), Modelsim (Mentor Graphics), Design Compiler, Prime Time (Synopsys).
    • Place and Route: Xilinx, Altera.
    • Board design (component selection, schematic entry, signal integrity, coordination of PCB layout, EMI/EMC, ESD, safety, test, follow-up manufacturing).
    • Pre and post layout signal integrity simulations by means of IBIS models.
    • Testing and debugging (oscilloscope, logic analyzer, pattern generator, BERT, …).

    PROFESSIONAL BACKGROUND

    Confidential (Belgium)   (Mar 2007 – Present)

    Sr. ASIC/DSP Design Engineer, Technical Lead

    As technical lead of a team working on a breakthrough high-performance A/D converter ASIC, responsible for:

    • Complete development cycle of the digital part (specification, design and modeling of digital corrections for analog impairments, bit true and cycle accurate C++ simulations, verification test plan and follow-up, prototyping on Xilinx platform, validation of silicon in system context).
    • Coordination of the technical design aspects and maintaining daily communication with the team in California that worked on the analog part of the ASIC.
    • Coaching of other team members and follow-up on contractors (VHDL coding, synthesis, verification).

    The tape-out was a big success and the ASIC is now a key component in Agilent's future spectrum analyzers. Promoted to Expert.

    The validation platform of the A/D converter was re-used to develop a complete real-time spectrum analysis and frequency mask triggering system for detecting and capturing transient signals with high probability of intercept. This involved:

    • Investigating customer requirements and defining an architecture which enables significant differentiation from competitors on the long term.
    • Specification, modeling in Simulink/System Generator, micro-architecture, design, simulation and testing.

    Part of the work was reported about in the European FP7 projects Samurai and Qosmos and were rated excellent at the review.

     

    Septentrio Satellite Navigation (Leuven, Belgium)   (Feb 2004 – Feb 2007)

    ASIC/FPGA Design Engineer

    Responsible for specification and design of a new architecture for a high-end, multi-frequency GNSS receiver ASIC.

    • Designed and simulated in VHDL multiple blocks (digital front-end with FIR filters, P/Y channel with adaptive semi-codeless controller, fast acquisition unit based on matched filter and FFT, …).
    • Prototyped a reduced channel GPS receiver in Xilinx Virtex II Pro (XC2VP40) and Virtex4 (XC4VLX40).
    • Integrated Xilinx’s MicroBlaze embedded processor with its peripherals (UART, interrupt controler,…) for test purposes and wrote C code for test applications for the embedded processor.

    The ASIC was first time right and is since then the core component of the AsteRx products.

    Responsible for the design of a new compact, low power architecture for a single frequency GPS/Galileo receiver targeted for lower cost in Xilinx Spartan3 (XC3S1000).

     

    Contracting and college (University of California Santa Cruz Extension)   (Sep 2002 –  Jan 2004)

    GlobespanVirata / iCompression (Santa Clara, California)  (Jan 2001 – Aug 2002)

    Hardware Engineer

    Responsible for ASIC prototyping for several ASICs used in VoIP applications.

    • Partitioned large complex designs among multiple FPGAs (one board had 8 Xilinx Virtex-II XC2V6000) and wrote Verilog code to support the integration and partitioning.
    • Performed synthesis, place and route, floorplanning and static timing analysis.
    • Debugged the ASIC code mapped in multiple FPGAs, in the lab with logic analyzer and oscilloscope.

    The prototyping allowed the ASIC designers to find problems in the chip, not encountered earlier during simulation, and saved over $500k for each tape-out iteration. Also, it created a platform for the DSP group to debug their software before the ASIC was available.

     

    Datax (Antwerp, Belgium)   (Jan 2000 – Dec 2000)

    Hardware Development Engineer

    Responsible for the entire development of the 2MCNV product, which provides an interface conversion between E1/T1 and X21, V35 or Ethernet.  This included:

    • Writing user requirements specification.
    • Feasibility study (board functionality, variants, physical constraints), power budget and cost analysis.
    • Evaluation of all required components and integrated circuits (analog and digital).
    • Design and simulation in VHDL (interface conversion, test loop handling,…), implemented in Altera’s MAX3000 series to achieve low cost at high volume.
    • Schematic capture, coordination of board layout and mechanical design.
    • Debug and test prototypes (EMI/EMC, ESD and compliancy tests), follow-up manufacturing.

     

    Alcatel (Antwerp, Belgium)   (Aug 1996 - Dec 1999)

    Hardware Design Engineer                                                                                                                                                   

    Designed high-speed ABCE board, which converts traffic from the broadband switch into ATM cells and extracts CBR traffic (composed of multiple E0, E1 connections), which is packed in a format suitable for narrow band. This included:

    • Feasibility study (board functionality, thermal behavior, floorplanning).
    • Writing design specification.
    • Schematic capture and follow-up board layout process.
    • Responsible for in-depth analysis of signal integrity by means of simulations and modeling (IBIS).
    • Debug and test prototypes.

    Participated in the architecture phase (feasibility study, processor evaluation,…) of high-speed ALK board, which terminates ATM cells and converts traffic towards the broadband switch. 

     

    Telkon (Antwerp, Belgium)   (Aug 1995 – Jun 1996)

    Internship + Final Thesis

    Developed and simulated a 16 QAM modem. This included the design of multiple digital filters using Matlab, and the development and implementation of several algorithms in C/C++.

     

    EDUCATIONAL BACKGROUND
     

    VLSI design engineering,University of California Santa Cruz Extension, USA. (2002-2003)

    Postgraduate degree in Telecommunications, IMEC Belgium (1997-1999)

    M.S. in Electrical Engineering, KIHO Belgium (1993-1996)

     

    Additional Training:

    Signal Processing with Simulink, Cambridge  (Dec 2011)               

    Comprehensive C++ (Doulos)  (Mar 2008)

    GPS Operation for Engineers & Technical Professionals (course 356)  (May 2005)

    EMC/EMI, TU Delft (Nov 1997)

     

    LANGUAGES

    Dutch: Mother tongue

    English: Excellent knowledge

    German: Intermediate knowledge

    French: Basic knowledge

     

    References:

    Available upon request.


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