Latest Space News
Wed, 20 Nov 2019 12:12:33 +0000
Commercial spaceports say they need to become more proactive in dealing with public opposition to proposed launch sites through a combination of education and community involvement. SpaceNews.com
Wed, 20 Nov 2019 10:40:05 +0000
Glavkosmos, the commercial subsidiary of Roscosmos, unveiled a web portal Nov. 20 for Russian rocket and space products. SpaceNews.com
Wed, 20 Nov 2019 09:32:22 +0000
The government of Brazil is ready to move into the next phase of efforts to attract commercial launch business to the country with the ratification of an agreement with the United States. SpaceNews.com
Tue, 19 Nov 2019 20:06:30 +0000
The report titled ”Iran Military Power” is part of a Defense Intelligence Agency effort to inform government leaders and the public on major foreign military challenges. SpaceNews.com
Tue, 19 Nov 2019 18:29:10 +0000
At the Space Tech Expo, space agency leaders said artificial intelligence will play key roles in many space programs of the future. SpaceNews.com
Tue, 19 Nov 2019 18:00:53 +0000
Dawn Harms, the former Boeing Satellite Systems International vice president for global sales and marketing, has joined Momentus to serve as chief revenue officer for the In-space transportation startup. SpaceNews.com
Tue, 19 Nov 2019 17:12:26 +0000
Portugal’s newly created space agency is considering a national constellation focused on maritime activity in the Atlantic Ocean.  SpaceNews.com
Tue, 19 Nov 2019 16:27:10 +0000
China Satcom has filed an insurance claim for the loss of a communications satellite after failing to establish contact with the spacecraft. SpaceNews.com
Tue, 19 Nov 2019 15:58:24 +0000
Rather than waiting for international consensus on measures to mitigate the problem of space debris, space agencies and companies should take immediate action, said Jan Woerner, European Space Agency director general. SpaceNews.com
Tue, 19 Nov 2019 12:26:30 +0000
Boeing said Nov. 18 that a report issued last week by NASA’s Office of Inspector General (OIG) regarding the commercial crew program, including claims that the company considered withdrawing from the program, was inaccurate. SpaceNews.com
Tue, 19 Nov 2019 12:11:16 +0000
Sweden, Germany, Italy, Scotland, Portugal and Norway all have spaceport ideas being discussed, OHB CEO Marco Fuchs said Nov. 19 at Space Tech Expo Europe here. SpaceNews.com
Tue, 19 Nov 2019 11:38:24 +0000
The European Commission is recommending a space budget of 16.2 billion euros ($17.9 billion) for 2021 through 2027, a nearly 50 percent increase over the 11 billion euros budgeted for 2014 through 2020. SpaceNews.com
Tue, 19 Nov 2019 04:50:22 +0000
NASA announced Nov. 18 that it was adding five companies to a contract to perform commercial deliveries of payloads to the surface of the moon, a group that ranges from small ventures to Blue Origin and SpaceX. SpaceNews.com
Mon, 18 Nov 2019 22:42:51 +0000
BREMEN, Germany — FCC Chairman Ajit Pai informed Congress Nov. 18 that the agency will run a public auction of C-band spectrum instead of allowing a consortium of satellite operators to sell it directly to 5G wireless operators.  Satellite operators Intelsat, SES and Telesat, acting as the C-Band Alliance, have been lobbying the Federal Communications […] SpaceNews.com
Mon, 18 Nov 2019 22:26:35 +0000
GAO said in a statement that the agency on Nov. 18 sustained the protest filed by Blue Origin on Aug. 12. SpaceNews.com
Mon, 18 Nov 2019 21:24:39 +0000
Gen. Raymond said U.S. SPACECOM intends to influence DoD's budget priorities SpaceNews.com
Mon, 18 Nov 2019 14:19:48 +0000
Satellite operators Intelsat, SES and Telesat on Nov. 15 detailed how they would calculate the proceeds they have pledged to contribute to the U.S. treasury if the Federal Communications Commission accepts their proposal to privately auction C-band spectrum sought by 5G network operators.  SpaceNews.com
Mon, 18 Nov 2019 10:10:29 +0000
A group of planetary defense advocates is asking European governments to fund a mission to a near Earth asteroid, three years after a similar mission failed to win approval. SpaceNews.com
Sun, 17 Nov 2019 23:42:07 +0000
Maj. Gen. Stephen Whiting said the transfer of space traffic management responsibilities can't happen until Commerce gets the necessary resources. SpaceNews.com
Fri, 15 Nov 2019 22:36:16 +0000
The 10-year contract is for operations and support of the Advanced Extremely High Frequency, Milstar and Defense Satellite Communications System constellations. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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