Latest Space News
Tue, 04 Aug 2020 11:34:44 +0000
Executives with several major small launch vehicle companies say both the economic repercussions of the pandemic and the growing interest by the U.S. government in such vehicles could reshape the industry. SpaceNews
Tue, 04 Aug 2020 10:02:28 +0000
Loft Orbital on Aug. 4 announced a contract to provide the spacecraft platform and arrange a launch for a Canadian quantum communications experiment.  SpaceNews
Mon, 03 Aug 2020 23:46:49 +0000
Virgin Galactic has pushed the beginning of commercial flights of its SpaceShipTwo suborbital vehicle to no earlier than the first quarter of 2021 while announcing plans to sell additional stock to raise money. SpaceNews
Mon, 03 Aug 2020 22:28:33 +0000
Michael O’Rielly had been nominated in March for a new five-year term as member of the Federal Communications Commission. SpaceNews
Mon, 03 Aug 2020 21:45:37 +0000
Army cadets at West Point learn how to build small satellites and rockets. Some also are considering competing to be a NASA astronaut. SpaceNews
Mon, 03 Aug 2020 21:10:22 +0000
Scolese said the NRO "will be able to do more with smaller satellites.” SpaceNews
Mon, 03 Aug 2020 20:02:06 +0000
A cubesat launched earlier this year has successfully tested a version of an instrument that will fly on a larger NASA mission in development. SpaceNews
Mon, 03 Aug 2020 18:41:07 +0000
Swarm Technologies is working with Exolaunch of Germany to send 24 SpaceBee satellites into orbit on the SpaceX Falcon 9 small satellite rideshare mission scheduled to launch in December. SpaceNews
Mon, 03 Aug 2020 18:27:20 +0000
Ball Aerospace says it has successfully flight-tested a green propellant developed by the Air Force, and is lowering the satellite’s altitude so that it deorbits in the coming weeks.  SpaceNews
Mon, 03 Aug 2020 18:00:33 +0000
Made In Space is underscoring national security applications for its in-space robotic assembly and additive manufacturing technologies at the annual Small Satellite Conference. SpaceNews
Mon, 03 Aug 2020 17:19:58 +0000
The French government awarded more than one million euros ($1.17 million) to Tououse-based Mecano ID to accelerate development of a small satellite deployer. SpaceNews
Mon, 03 Aug 2020 16:00:36 +0000
In-space transportation startup Momentus announced plans Aug. 3 to begin flying hosted payloads for customers in 2021. SpaceNews
Mon, 03 Aug 2020 13:56:55 +0000
Download your digital edition of the Aug. 3 issue of SpaceNews magazine, provided to you free as part of our special coverage of this week's free-to-attend 34th Annual Small Satellite Conference.  SpaceNews
Mon, 03 Aug 2020 13:00:54 +0000
SpaceBel, a space systems and software company, will seek to raise around 10 million euros ($11.8 million) in 2021 to initiate development of the constellation and prepare for a demonstration satellite launch in 2023. SpaceNews
Mon, 03 Aug 2020 08:00:22 +0000
ABL says the funding will accelerate the development of its two-stage launch vehicle and mobile infrastructure. SpaceNews
Mon, 03 Aug 2020 05:40:40 +0000
General Atomics Electromagnetic Systems won a $32.9 million contract to build NASA’s Total and Spectral solar Irradiance-2 (TSIS-2) spacecraft, a small satellite scheduled to launch in 2023. SpaceNews
Mon, 03 Aug 2020 02:22:44 +0000
Raytheon Intelligence & Space is designing a prototype weather satellite for the U.S. Space Force Space and Missile Systems Center that draws heavily on technology from the firm’s Visible Infrared Imaging Radiometer Suite and Moderate Resolution Imaging Spectroradiometer. SpaceNews
Sun, 02 Aug 2020 19:10:02 +0000
SpaceX’s Crew Dragon spacecraft splashed down in the Gulf of Mexico Aug. 2, successfully completing a test flight and crossing the finish line of the decade-long commercial crew program. SpaceNews
Sun, 02 Aug 2020 16:52:04 +0000
Japanese company ispace has updated the design of its commercial lunar lander while delaying its first flight by a year. SpaceNews
Sun, 02 Aug 2020 00:09:07 +0000
A SpaceX Crew Dragon spacecraft carrying two NASA astronauts on a test flight undocked from the International Space Station Aug. 1 ahead of a splashdown less than 24 hours later. SpaceNews
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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