Latest Space News
Wed, 10 Aug 2022 04:11:20 +0000
Blue Canyon Technologies won its largest constellation order to date, a contract with weather technology company Tomorrow.io.  The post Blue Canyon Technologies to build Tomorrow.io constellation appeared first on SpaceNews.
Wed, 10 Aug 2022 03:49:05 +0000
After a series of spaceflight demonstrations followed by years of secrecy, Novawurks is ready to talk contracts, customers and expansion plans.  The post NovaWurks reveals contracts, expansion plans and Space Legos appeared first on SpaceNews.
Wed, 10 Aug 2022 01:04:46 +0000
Gen. James Dickinson, head uf U.S. Space Command, said space traffic management should be transferred to a civilian agency as soon as possible The post Tracking debris and space traffic a growing challenge for U.S. military appeared first on SpaceNews.
Tue, 09 Aug 2022 22:19:05 +0000
The head of U.S. Space Command said he expects a final decision to be made relatively soon on where the command will be permanently headquartered. The post U.S. Space Command basing decision approaching final stretch appeared first on SpaceNews.
Tue, 09 Aug 2022 21:57:15 +0000
Italy’s D-Orbit said Aug. 9 that it would launch 20 nanosatellites over three years for Swiss startup Astrocast with its orbital transfer vehicle. The post D-Orbit to deploy 20 Astrocast satellites over three years appeared first on SpaceNews.
Tue, 09 Aug 2022 21:32:09 +0000
Maxar Technologies announced Aug. 9 it was selected by L3Harris to manufacture 14 missile-detection satellites for the U.S. Space Development Agency. The post Maxar to supply 14 satellites for U.S. military missile-tracking constellation appeared first on SpaceNews.
Tue, 09 Aug 2022 20:30:55 +0000
The Aerospace Corp. is establishing a network of remotely operated optical communications terminals to support existing and future small satellite missions. The post Aerospace develops low-cost optical ground network appeared first on SpaceNews.
Tue, 09 Aug 2022 19:59:23 +0000
SpaceX, whose rideshare services have reshaped the smallsat launch market, says it continues to see strong demand with missions booked into 2025. The post SpaceX sees continued strong demand for rideshare missions appeared first on SpaceNews.
Tue, 09 Aug 2022 19:14:14 +0000
Atlas Space Operations upgraded its user interface to make it easier for customers to schedule communications with their satellites and to quickly confirm whether data was transmitted. The post Atlas Space Operations upgrades user interface to ease scheduling appeared first on SpaceNews.
Tue, 09 Aug 2022 19:09:14 +0000
Telespazio is beginning to offer a family of products to help commercial space companies set up a digitized ground segment in the cloud. The post Telespazio unveils product line for NewSpace market appeared first on SpaceNews.
Tue, 09 Aug 2022 18:18:08 +0000
Sidus Space could launch LizzieSat-1 without thrusters if it can’t get safety clearances in time to deploy its first satellite from the International Space Station early next year. The post Sidus Space could launch LizzieSat-1 without thrusters appeared first on SpaceNews.
Tue, 09 Aug 2022 17:07:39 +0000
The SpaceNews editorial team is producing a daily for the 2022 Small Satellite show, a nightly email newsletter and all-day web coverage during the 2022 Small Satellite show in Logan, Utah the week of August 9. The post Download your Tuesday ‘News from the 2022 Small Satellite show’ digital edition appeared first on SpaceNews.
Tue, 09 Aug 2022 17:00:50 +0000
Small satellite manufacturer Terran Orbital reported increased revenues Aug. 9 as it ramps up work on satellites for the Space Development Agency, but is planning to sell stock as its cash reserves decline. The post Terran Orbital prioritizes work on SDA smallsats over PredaSAR appeared first on SpaceNews.
Tue, 09 Aug 2022 15:17:36 +0000
Debris from a Russian antisatellite weapon demonstration that caused “squalls” of close approaches to satellites earlier this year is now affecting a new series of Starlink satellites. The post Starlink satellites encounter Russian ASAT debris squalls appeared first on SpaceNews.
Tue, 09 Aug 2022 12:00:08 +0000
Busek is rapidly expanding its staff and facilities in response to strong demand for spacecraft propulsion. The post Busek finds headroom to double in size appeared first on SpaceNews.
Tue, 09 Aug 2022 10:40:38 +0000
Chinese commercial launch service provider Galactic Energy maintained a 100 percent launch record early Tuesday with its third Ceres-1 solid rocket launch. The post Galactic Energy of China registers third consecutive successful launch appeared first on SpaceNews.
Tue, 09 Aug 2022 10:00:00 +0000
Space logistics startup TransAstronautica announced a partnership Aug. 9 with online astronomy platform Slooh to offer U.S. schools access to a global telescope network of ground-based and space-based telescopes. The post TransAstra and Slooh to offer students asteroid detection tool appeared first on SpaceNews.
Tue, 09 Aug 2022 07:00:48 +0000
Benchmark Space Systems unveiled a collision avoidance kit designed to help small satellites dodge debris and steer clear of other spacecraft. The post Benchmark unveils small satellite collision-avoidance kit appeared first on SpaceNews.
Mon, 08 Aug 2022 21:21:52 +0000
Canadian launch startup SpaceRyde said Aug. 8 it has added a second member to its advisory board with the appointment of Mina Mitry, the CEO of small satellite operator Kepler Communications. The post Launch startup SpaceRyde fortifies advisory board appeared first on SpaceNews.
Mon, 08 Aug 2022 21:10:12 +0000
Rocket Lab’s launch of a NASA lunar cubesat mission lived up to its name, serving as a capstone for the company’s efforts to develop end-to-end space systems and interplanetary missions, according to its chief executive. The post Beck: CAPSTONE demonstrates feasibility of low-cost interplanetary smallsats appeared first on SpaceNews.
More space news...
20728 cvs - 1192 jobs

LOOKING FOR A JOB?

  • HOME
  • POST YOUR CV
  • JOB SEARCH
  • LOOKING FOR STAFF?

  • HOME
  • REGISTER
  • CV SEARCH
  • POST JOBS
  • CV: Design engineer

    Printer Friendly


    << BACK

    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
     Mobile:<withheld>
    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


    Registering is the only way of posting vacancies and obtaining contact details of candidates in our CV database.

    All it takes is a few minutes and a credit card (Visa or American Express). To sign-up to this service, simply click on the Register link and fill in the form. You will then have instant access to our system after on-line payment where you will be able to complete the transaction in either US Dollars, UK Pounds or Euros.

    All online credit/debit card transitions are handled through our secure third party payment processors at WorldPay. Worldpay are part of The Royal Bank of Scotland Group, the 5th biggest banking group in the world, WorldPay payment solutions are trusted by thousands of businesses, big and small worldwide. 

    Pricing starts at €450 (approx £400 or US$500 - use the convert tool for an exact conversion) for one month unlimited job postings and unlimited CV database access (for one user), with package discounts available if you have more permanent recruiting needs.

     

    2022 Pricing Structure (excluding VAT):

    1 month - Discovery 450 euros convert
    3 months - Bronze 1150 euros convert

     

    If online payment is not convenient, give us a call at +33(0)622757477 or send us an email at sales@space-careers.com. We will set up an account for you and invoice you, but in this case, access to our website will be granted only after payment has been received. Note that you can also pay through PayPal.

     

    Subscriptions

     

    Please note that the posting of academic positions is free of charge. All you need to do is email us your job description and we will post it for you.

     

    VAT:

    Spacelinks is based in France so the following European Union regulations regarding electronic commerce apply:
    - if your business is located outside the EU, VAT does not apply to you
    - if your business is located in France, you will be charged a 20% VAT
    - if your business is located in the EU and you don't have a valid VAT registration number, you will be charged a 20% VAT
    - if your business is located in the EU and you do have a valid VAT registration number, you won't be charged VAT provided you give us your VAT number (mandatory for invoicing)

     

    Support:

    For sales enquiries and general information, you can call us on +33(0)622757477.
    Support is available Mon-Fri on +33(0)622757477 or via email. Out-of-hours support is provided only via email.

    Please also note that we are located in France. Our normal office hours are 09:00 to 18:00 Monday to Friday. France timezone is GMT+1.

     

    Warning:

    We are very serious about our job seekers privacy so only legitimate recruiters and employers are eligible for a recruiter account. All subscriptions requests will be manually approved and recruiter accounts constantly monitored. Users who enter inaccurate or incomplete information will not gain access to post jobs or search resumes. Sharing of login details with a third party will result in the suspension of the recruiter's account with no subscription refund.

    To ensure you are approved, please include the following on your application:
    * The website address of your Company. Under construction websites will be rejected.
    * Email - Must end in @yourcompany.com. Applications using free email accounts such as Hotmail, Yahoo or Gmail will be rejected.

    Individual exceptions can be made on a case by case basis by emailing sales@space-careers.com. Accounts found not to be in compliance will be deleted.

     
    Terms & ConditionsCopyright ©2022 Spacelinks
    Web Analytics