Latest Space News
Sat, 16 Dec 2017 15:25:25 +0000
Stymied by poor weather and technical glitches, including one that aborted a launch just two seconds before liftoff, Rocket Lab said Dec. 16 it will delay its next Electron launch attempt until early 2018. SpaceNews.com
Fri, 15 Dec 2017 21:51:14 +0000
NASA expects to purchase Earth science data from constellations of commercial satellites early next year to see how useful they are in meeting the agency’s research needs. SpaceNews.com
Fri, 15 Dec 2017 21:03:48 +0000
German satellite builder OHB Systems has secured a slot for the experimental Heinrich Hertz communications satellite on what could be one of the last Ariane 5 missions before Ariane 6 is expected to take over. SpaceNews.com
Fri, 15 Dec 2017 16:38:44 +0000
A 99 million pound ($132 million) satellite test facility to be built at the U.K.’s Harwell Campus should bring more business to the space hub here and ensure Britain’s satellite manufacturers can carry on without disruption post-Brexit, according to Chris Mutlow, director of RAL Space, the space division of the U.K. state-run Rutherford Appleton Laboratory here. SpaceNews.com
Fri, 15 Dec 2017 16:37:29 +0000
A SpaceX Falcon 9 successfully launched a Dragon cargo spacecraft to the International Space Station Dec. 15 on the first use of a previously-flown first stage for a NASA mission. SpaceNews.com
Fri, 15 Dec 2017 11:33:25 +0000
Thales Alenia Space is partnering with three U.S. companies that are working on NASA studies of concepts for the proposed Deep Space Gateway, leveraging its expertise in space station and cargo module development. SpaceNews.com
Thu, 14 Dec 2017 22:48:52 +0000
AIA CEO Melcher: “I’m very concerned about how our nation has come to accept several anchors that are dragging our industry down" SpaceNews.com
Thu, 14 Dec 2017 21:42:28 +0000
Airbus has signed a contract with the European Space Agency to develop a Copernicus Data and Information Access Services, orDIAS, platform that will make data from the Earth-monitoring constellation more accessible to users from about mid-2018. SpaceNews.com
Thu, 14 Dec 2017 16:57:56 +0000
SpaceIL, the Israeli team in the Google Lunar X Prize competition, says it needs to raise $7.5 million in less than a week in order to complete its lander and retain its launch contract. SpaceNews.com
Thu, 14 Dec 2017 11:00:27 +0000
NASA’s Dawn mission to the main asteroid belt, granted a second extended mission earlier this year, will end later next year after a final set of close-up observations of the dwarf planet Ceres. SpaceNews.com
Thu, 14 Dec 2017 01:59:27 +0000
Lockheed envisions many uses for artificial intelligence in space, such as being able to quickly detect changes in satellite performance and in the environment. SpaceNews.com
Wed, 13 Dec 2017 18:53:09 +0000
The Senate Commerce Committee advanced the nomination of Barry Myers to be the next administrator of NOAA to the full Senate despite concerns by the committee’s Democrats about potential conflicts of interest. SpaceNews.com
Wed, 13 Dec 2017 10:08:47 +0000
A Japanese company planning a series of robotic missions to the moon announced Dec. 13 that it has raised more than $90 million in one of the largest Series A funding rounds for any emerging space venture. SpaceNews.com
Wed, 13 Dec 2017 08:47:31 +0000
Blue Origin said it carried out a successful test flight of a new version of its New Shepard suborbital vehicle Dec. 12. SpaceNews.com
Wed, 13 Dec 2017 04:06:57 +0000
Arianespace performed its eleventh and final launch of the year today, sending four Galileo European navigation satellites into medium Earth orbit. SpaceNews.com
Tue, 12 Dec 2017 20:39:55 +0000
The new decadal survey for Earth science research will likely be unveiled in early January, slightly later than previously planned. SpaceNews.com
Tue, 12 Dec 2017 20:17:22 +0000
The U.S. Federal Communications Commission on Dec. 5 okayed the first part of a satellite-servicing mission Orbital ATK’s Space Logistic subsidiary has with Intelsat, saying the servicing vehicle can execute “rendezvous, proximity operations, and docking with the Intelsat-901” satellite while in a graveyard orbit. SpaceNews.com
Tue, 12 Dec 2017 17:20:18 +0000
Tucked into the details of the 2018 National Defense Authorization Act that President Trump signed into law Dec. 12 is a long overdue recognition of the first American astronauts who were lost in service to their country while practicing for a mission. SpaceNews.com
Tue, 12 Dec 2017 11:41:15 +0000
Rocket Lab scrubbed a launch of its Electron small launch vehicle Dec. 11 after an abort just two seconds before liftoff. SpaceNews.com
Tue, 12 Dec 2017 03:55:05 +0000
President Trump’s new space policy directive calling for American astronauts to return to the moon is welcome and encouraging news. SpaceNews.com
More space news...
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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