Latest Space News
Fri, 22 Jun 2018 22:07:52 +0000
Nearly a month after the signing of a policy directive calling for commercial space regulatory reforms, Commerce Department officials said this week they’re moving ahead on a number of fronts. SpaceNews.com
Fri, 22 Jun 2018 03:12:12 +0000
The White House has directed NASA to study the possibility of converting one of more of its field centers into federal labs, revisiting a proposal made nearly 15 years ago. SpaceNews.com
Fri, 22 Jun 2018 00:04:04 +0000
The Falcon Heavy beat United Launch Alliance’s Delta 4 in a competition under the Evolved Expendable Launch Vehicle program. SpaceNews.com
Thu, 21 Jun 2018 23:41:21 +0000
To receive FIRST UP Satcom, a weekly SpaceNews newsletter for satellite and telecom professionals, sign up here. TOP STORIES Chinese hackers tried to gain control of U.S. satellites in late 2017, leading a cyber firm to notify the U.S. government. Symantec’s protection software blocked some of the tools used by attackers known as “Thrip” that attacked two […] SpaceNews.com
Thu, 21 Jun 2018 22:56:40 +0000
Blue Origin expects to start flying people on its New Shepard suborbital vehicle “soon” and start selling tickets for commercial flights next year, a company executive said June 19. SpaceNews.com
Thu, 21 Jun 2018 21:41:59 +0000
Canadian satellite antenna manufacturer C-Com said June 21 it successfully tested the building blocks of a phased array antenna it hopes to sell next year. SpaceNews.com
Thu, 21 Jun 2018 15:25:18 +0000
Rogers: Whether you call the new branch a Space Corps or a Space Force is not all that important. SpaceNews.com
Thu, 21 Jun 2018 10:45:26 +0000
A report released by the White House June 20 outlines a set of goals to address the small but “high-consequence” threat posed by near Earth objects (NEOs), but does not commit to spending more money to achieve them. SpaceNews.com
Wed, 20 Jun 2018 19:52:56 +0000
Former Air Force Secretary Deborah Lee James: "The Air Force and the DoD have to come up with something to back up what the president said.” SpaceNews.com
Wed, 20 Jun 2018 15:57:18 +0000
China has lowered the orbit of its Tiangong-2 space lab, likely in preparation for deorbiting the orbital facility and thus averting a similar scenario to the uncontrolled re-entry of Tiangong-1 earlier this year. SpaceNews.com
Wed, 20 Jun 2018 12:13:10 +0000
Those who loathe or love a Space Force “separate but equal” to the Air Force must think and act decisively and quickly. Regardless of whether the Space Force actually materializes, deliberation alone could finally spring us into action to deal with the looming threat of space Pearl Harbor. SpaceNews.com
Wed, 20 Jun 2018 11:12:05 +0000
An advisory group dubbed the “think tank” for the National Space Council formally kicked off its work June 19 with a broad but vague mandate to study space policy issues. SpaceNews.com
Wed, 20 Jun 2018 00:08:21 +0000
Fleet operators SES and Intelsat asked the U.S. Federal Communications Commission to extend the deadline for their customers to register C-band dishes before the commission decides on the band’s future use. SpaceNews.com
Tue, 19 Jun 2018 11:00:08 +0000
Trump’s proposal derives from a growing debate inside military and political circles about how to best meet the threat posed to American space assets by potential enemies: Russia and China, to be precise. SpaceNews.com
Tue, 19 Jun 2018 01:45:44 +0000
A former NASA astronaut used an appearance at a National Space Council meeting June 18 to argue that a key element of NASA’s plans to return humans to the moon should be reconsidered. SpaceNews.com
Mon, 18 Jun 2018 19:35:34 +0000
Trump: Creating a Space Force and promoting space exploration by NASA and the private sector will be “important for the nation’s psyche.” SpaceNews.com
Mon, 18 Jun 2018 13:22:16 +0000
President Trump will sign a new space policy directive June 18 addressing space traffic management issues, closely following the proposed policy that Vice President Pence announced in April. SpaceNews.com
Mon, 18 Jun 2018 08:45:21 +0000
A key senator says he’s keeping an open mind regarding who in the federal government should have responsibility for the oversight of “non-traditional” commercial space activities. SpaceNews.com
Sat, 16 Jun 2018 19:45:35 +0000
The House Appropriations defense subcommittee approved $49.5 million to create a new “program of record for commercial satellite communications." SpaceNews.com
Fri, 15 Jun 2018 20:23:14 +0000
As the National Space Council prepares for its third public meeting, its activities to date have won widespread praise in the space community, even as there is some skepticism about the effectiveness of the council’s advisory group that will soon meet for the first time. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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