Latest Space News
Wed, 25 Apr 2018 01:25:18 +0000
Air Force Secretary Heather Wilson made news last week at the Space Symposium with major announcements on the reorganization of Space and Missile Systems Center and the standup of a new office to eliminate bottlenecks in the system. SpaceNews.com
Wed, 25 Apr 2018 01:11:07 +0000
Iceye, the Finnish company flying a Synthetic Aperture Radar (SAR) microsatellite, forged an alliance with Ursa Space Systems, a firm that offers economic insights from geospatial data. SpaceNews.com
Tue, 24 Apr 2018 21:20:22 +0000
Countering WMDs is a major intelligence fusion challenge. Thomas: “Even for an organization that prides itself in agility, which we do, this is some incredibly problem solving.” SpaceNews.com
Tue, 24 Apr 2018 20:23:58 +0000
Geospatial data companies are focusing intently on acquiring satellite imagery quickly and speeding data delivery to customers. SpaceNews.com
Tue, 24 Apr 2018 20:14:24 +0000
The light-lift Vega rocket is Europe’s vehicle of choice for small satellites, but has mainly launched spacecraft weighing hundreds of kilograms. While that’s smaller than what Arianespace normally launches on an Ariane 5 or Soyuz, it’s not the “small” that people generally think of when they think smallsats. SpaceNews.com
Tue, 24 Apr 2018 18:09:21 +0000
Lockheed Martin executives said April 24 they are confident they will win an Air Force competition for the next set of GPS 3 navigation satellites as questions swirl about what other companies, if any, submitted proposals. SpaceNews.com
Tue, 24 Apr 2018 15:42:28 +0000
An Ariane 5 launch has been cancelled after an unexplained problem with an Indian space agency satellite that was supposed to ride on the mission. SpaceNews.com
Tue, 24 Apr 2018 14:34:24 +0000
In its quest for cutting edge commercial solutions to military problems, the U.S. Defense Innovation Unit Experimental (DIUx) is not ignoring the talents of traditional government contractors. SpaceNews.com
Tue, 24 Apr 2018 02:47:23 +0000
Speedcast’s revenues more than doubled in 2017 as the satellite network operator began leveraging its acquisitions of U.S. companies Harris CapRock and UltiSat. SpaceNews.com
Tue, 24 Apr 2018 01:18:18 +0000
NGA Director Cardillo: “I want the market to work … but government shouldn’t be their first customer. We should be their second customer.” SpaceNews.com
Mon, 23 Apr 2018 23:00:57 +0000
NASA’s new administrator said he’s “very excited” about leading the space agency as he takes office after an extended confirmation process. SpaceNews.com
Mon, 23 Apr 2018 19:24:12 +0000
USD Kernan: "we really haven’t taken all the advantage we can of technology.” SpaceNews.com
Mon, 23 Apr 2018 19:01:42 +0000
Wilson sat down with SpaceNews at the recent Space Symposium in Colorado Springs to discuss the ongoing reorganization of the Space and Missile Systems Center, space investment priorities and her plans to secure congressional support for budgets and management reforms. SpaceNews.com
Mon, 23 Apr 2018 17:54:23 +0000
In the months preceding the launch of Avanti’s Hylas-4 satellite, the British operators didn’t mince words when it described the importance of a successful mission as “critical.” SpaceNews.com
Mon, 23 Apr 2018 12:23:19 +0000
"We are trying to effectively link air, land, sea and space. The geospatial context on the ground may give you some type of indications and warning of something happening in space," said Chirag Parikh, director of NGA's Office of Source Strategies. SpaceNews.com
Mon, 23 Apr 2018 00:53:45 +0000
NASA’s next administrator, Jim Bridenstine, is set to be sworn into office April 23 as the space industry breathes a sigh of relief that his extended confirmation process is finally over. SpaceNews.com
Sun, 22 Apr 2018 23:31:54 +0000
Within the top five space contractors, from 2011 to 2017, ULA surpassed Boeing and became the top overall vendor. SpaceNews.com
Sat, 21 Apr 2018 16:53:32 +0000
"Other transactions authorities" allow the Air Force to go faster to prototyping. SpaceNews.com
Fri, 20 Apr 2018 23:19:54 +0000
GEOShare, a Lockheed Martin subsidiary matching missions with orbital slots in an effort to boost satellite sales, has signed up over 150 missions and over 100 orbital locations, said Lon Levin, GEOShare president and chief executive. SpaceNews.com
Fri, 20 Apr 2018 16:46:40 +0000
As Lockheed Martin prepares to complete assembly of the Orion spacecraft flying on the first SLS mission, the company says it’s making progress in lowering the costs of the future spacecraft, including through reuse. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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