Latest Space News
Thu, 16 Aug 2018 05:05:34 +0000
Descartes Labs announced Aug. 15 a partnership with Airbus to feed high resolution global imagery into its geospatial data platform. The Sante Fe, New Mexico-based startup also completed beta testing of its cloud-based “data refinery,” and added weather data. SpaceNews.com
Thu, 16 Aug 2018 00:21:09 +0000
International mistrust in space could become a bigger problem as the commercial space industry continues to grow and demand a peaceful environment to do business. SpaceNews.com
Wed, 15 Aug 2018 22:55:18 +0000
NASA says an Aug. 14 test of an engine for the Space Launch System was a success despite an unspecified “facility issue” that caused the test to end early. SpaceNews.com
Wed, 15 Aug 2018 18:18:44 +0000
ESA is pushing European industry to continue innovating and finding efficiencies even after Vega C’s introduction in 2019 and Ariane 6’s debut in 2020. SpaceNews.com
Wed, 15 Aug 2018 18:13:20 +0000
China will launch its Chang’e-4 lander and rover mission in December in what will be the first ever attempt at a soft landing on the far side of the moon, authorities said Aug. 15 SpaceNews.com
Tue, 14 Aug 2018 23:33:39 +0000
NASA has done a good job implementing the recommendations of its latest planetary science decadal survey despite past budget problems, but needs to improve some programs, a recent report concluded. SpaceNews.com
Tue, 14 Aug 2018 22:04:46 +0000
The Air Force will use “rapid procurement authorities” in this program and is targeting the first next-generation OPIR launch in 2023. SpaceNews.com
Tue, 14 Aug 2018 21:57:09 +0000
The Pentagon's Joint Oversight Requirements Council will be briefed this fall on potential solutions to a major national security vulnerability: hypersonic weapons that fly into space at supersonic speeds and descend back down to Earth directly on top of targets. SpaceNews.com
Tue, 14 Aug 2018 13:42:54 +0000
Chinese private launch vehicle maker OneSpace has secured $43.6 million in Series B financing as the company looks to its first orbital launch near the end of 2018. SpaceNews.com
Tue, 14 Aug 2018 00:32:25 +0000
Exos Aerospace, a Texas company developing a reusable suborbital rocket, now plans to carry out a first flight of its vehicle in late August as it sets its sights on a follow-on orbital vehicle. SpaceNews.com
Mon, 13 Aug 2018 19:50:09 +0000
Viasat is still working on a medium-Earth-orbit satellite constellation idea revealed almost two years ago, but has not finalized what that system would look like, Mark Dankberg, CEO of Viasat, said Aug. 9. SpaceNews.com
Mon, 13 Aug 2018 03:47:45 +0000
At the annual SMI MilSatCom Conference in 2017, Army Major General Pete Gallagher, former CENTCOM/J6, shared a vignette about U.S. forces fighting ISIS in the CENTCOM Area of Responsibility. SpaceNews.com
Sun, 12 Aug 2018 19:19:58 +0000
Griffin: "The bumper sticker version of my job is that I don’t have anything to do with anything that the Defense Department is currently buying. " SpaceNews.com
Sun, 12 Aug 2018 08:27:36 +0000
A NASA mission to travel closer to the sun than any previous spacecraft is on its way after a successful launch from Cape Canaveral Aug. 12. SpaceNews.com
Sun, 12 Aug 2018 00:07:38 +0000
Deputy Defense Secretary Patrick Shanahan: “It's going to take some time to work this through the Congress." SpaceNews.com
Fri, 10 Aug 2018 22:16:21 +0000
NASA announced more than 20 contracts valued at $55 million Aug. 8 intended to develop commercial technologies for space exploration as well as study future markets for commercial activities in low Earth orbit. SpaceNews.com
Fri, 10 Aug 2018 02:29:36 +0000
Small satellites that have propulsion systems, but don’t have encrypted commanding systems, pose a small but real threat of being hacked and endangering other satellites, according to a new study. SpaceNews.com
Fri, 10 Aug 2018 02:14:18 +0000
French fleet operator Eutelsat sold a jointly-owned satellite to partner Es’hailSat of Qatar, expanding Es’hailSat’s fleet as the company awaits the launch of its second satellite late this year on a Falcon 9 rocket. SpaceNews.com
Fri, 10 Aug 2018 02:04:16 +0000
Jim Simpson, chief executive of Bermuda-based fleet operator ABS since December, is no longer head of the company. SpaceNews.com
Fri, 10 Aug 2018 00:18:26 +0000
Why was the DoD space reorganization report more than a week late? The White House ordered a few tweaks. SpaceNews.com
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  • CV: Design engineer

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    Personal information
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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