Latest Space News
Mon, 10 Dec 2018 18:27:02 +0000
Aerospace CEO Isakowitz: The government traditionally buys a bus, payload and ground segment as a package, he said. That does not give you flexibility to swap out and change pieces. SpaceNews.com
Mon, 10 Dec 2018 17:32:45 +0000
As NASA’s Voyager 2 spacecraft enters interstellar space, project officials have high hopes that it and its twin spacecraft will continue to operate for as long as a decade. SpaceNews.com
Mon, 10 Dec 2018 17:17:23 +0000
Spacecraft manufacturers have complained of stress on their supplier base as operators purchase fewer traditional geostationary satellites. One company in France is bucking that trend, however. SpaceNews.com
Mon, 10 Dec 2018 11:27:24 +0000
A NASA spacecraft originally built as part of the previous effort to return humans to the moon is now playing a key role in the new effort at human lunar return, including aiding commercial landers. SpaceNews.com
Sun, 09 Dec 2018 12:25:35 +0000
In recent years, there has been a boom of announcements for satellite constellations comprising satellites weighing as little as 3 kilograms to address a growing market of machine-to-machine (M2M) and Internet of Things (IoT) via satellite. SpaceNews.com
Fri, 07 Dec 2018 23:03:07 +0000
In an interview, Axelspace Chief Business Development Officer Yasunori Yamazaki, said the funding will enable the company of 65 people to continue building a constellation called AxelGlobe, though the company hasn’t decided on a final size for the constellation. SpaceNews.com
Fri, 07 Dec 2018 22:32:49 +0000
With a two-week extension of the stopgap spending bill funding much of the federal government enacted, the outgoing chairman of the House appropriations subcommittee that funds NASA says he’s hopeful to get a final spending bill approved before that bill expires. SpaceNews.com
Fri, 07 Dec 2018 21:09:10 +0000
China launched its Chang’e-4 moon mission Dec. 7, successfully sending the lander and rover into a lunar transfer orbit ahead of an unprecedented attempt at a landing on the far side of the moon early in the New Year. SpaceNews.com
Fri, 07 Dec 2018 20:17:37 +0000
The new launch date, announced Dec. 7 by customer Iridium Communications, was driven by the additional two weeks SpaceX ended up needing to launch Spaceflight Industries’ “SmallSat Express” dedicated rideshare mission. SpaceNews.com
Fri, 07 Dec 2018 12:03:51 +0000
While a SpaceX commercial crew test flight might not launch on a date in early January previously announced NASA, both agency and company officials are optimistic the mission will still fly later in the month. SpaceNews.com
Thu, 06 Dec 2018 23:10:23 +0000
During a Q&A session at a U.S. Chamber of Commerce summit to promote the space industry as an engine of innovation and economic growth, Griffin said he does not know when or how a new military branch will be organized. SpaceNews.com
Thu, 06 Dec 2018 21:55:50 +0000
Maxar Technologies sold one of satellite manufacturer Space Systems Loral’s facilities in Silicon Valley for $70 million, the company announced today. SpaceNews.com
Thu, 06 Dec 2018 21:34:19 +0000
A test flight in Alaska of a small launch vehicle by a stealthy startup company ended in failure in late November, the FAA has revealed. SpaceNews.com
Thu, 06 Dec 2018 21:19:28 +0000
President Trump has been insistent that a Space Force should be a completely independent military department. One way to organize the new service would be by establishing a Space Force under a larger Department of the Air and Space Force. SpaceNews.com
Thu, 06 Dec 2018 18:42:11 +0000
British satellite operator Inmarsat announced Dec. 5 it will be the first commercial customer of the next-generation H3 rocket from Mitsubishi Heavy Industries of Japan. SpaceNews.com
Wed, 05 Dec 2018 23:52:27 +0000
The failure of a Falcon 9 first stage to make its planned landing after a Dec. 5 launch shouldn’t affect plans for upcoming launches, a SpaceX executive said. SpaceNews.com
Wed, 05 Dec 2018 22:54:52 +0000
European satellite manufacturer Thales Alenia Space said Dec. 5 it signed separate contracts with Korean Aerospace Industries (KAI) and Hanwha Systems Corp. to develop four high-resolution radar satellites for South Korea’s Agency for Defence Development. SpaceNews.com
Wed, 05 Dec 2018 18:58:25 +0000
On the company’s 20th mission of the year and second within 48 hours, SpaceX successfully launched a Dragon cargo spacecraft to the International Space Station Dec. 5, but suffered a rare failed landing of the rocket’s first stage. SpaceNews.com
Wed, 05 Dec 2018 17:22:41 +0000
The founders of Globa IP said they left after concerns its investors, supported by the Chinese government, were using the company as a means to gain access to satellite technology prohibited for export to China under U.S. law. SpaceNews.com
Wed, 05 Dec 2018 15:18:45 +0000
U.S. Air Force Secretary Heather Wilson, the winner of SpaceNews' 2018 military space Government Leader of the Year award, said as the Trump administration moves forward with plans to create a new military branch for space — an effort she supports — the Air Force is keeping focused on the space mission. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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