Latest Space News
Thu, 25 Apr 2019 22:02:07 +0000
As NASA studies ways to accelerate development of the Space Launch System, an independent safety panel called on the agency to retain a major upcoming test of the vehicle. SpaceNews.com
Thu, 25 Apr 2019 21:51:50 +0000
The United States should do more to protect its space systems and build capabilities as a form of deterrence, experts said. SpaceNews.com
Thu, 25 Apr 2019 17:41:03 +0000
U.K. Export Finance, an agency with a long-standing interest in supporting satellite projects but with little to show for it until now, has signed a $325 million loan with Turkey to support two satellites Airbus is building under a 2017 contract. SpaceNews.com
Thu, 25 Apr 2019 17:29:59 +0000
Members of an independent safety panel said it will take time to determine what happened during a SpaceX Crew Dragon testing incident several days ago, and that its impact to the overall commercial crew program remains uncertain. SpaceNews.com
Thu, 25 Apr 2019 16:29:18 +0000
DoD IG report says Musk told Shanahan that SpaceX did not win an Air Force launch service contract because it had written a poor proposal that “missed the mark.” SpaceNews.com
Thu, 25 Apr 2019 00:09:42 +0000
Nearly a year after Northrop Grumman’s acquisition of Orbital ATK closed, company executives say they’re getting the benefits they expected from the deal in terms of cost savings and new business. SpaceNews.com
Wed, 24 Apr 2019 21:26:12 +0000
Seven states have National Guard space units: Alaska, California, Colorado, Florida, New York, Arkansas and Ohio. SpaceNews.com
Wed, 24 Apr 2019 21:00:46 +0000
The Air Force 45th Space Wing is gearing up for three high-profile space launches at Cape Canaveral over the coming months. SpaceNews.com
Wed, 24 Apr 2019 18:57:50 +0000
The Justice Department has reached a settlement with the company that provided faulty components that led to the failure of back-to-back Taurus launches for NASA. SpaceNews.com
Wed, 24 Apr 2019 18:44:24 +0000
The reason for the Atlas 5 upper stage break up, believed to have occurred between March 23 and March 25, is not yet known. SpaceNews.com
Wed, 24 Apr 2019 03:16:54 +0000
As NASA works to develop a plan for an accelerated human return to the moon, a top White House official emphasized the need for long-term sustainability that will require both a Gateway and a lunar base. SpaceNews.com
Wed, 24 Apr 2019 00:14:56 +0000
Kitay: Actions in space “will directly affect the outcome of future conflicts or crises." SpaceNews.com
Tue, 23 Apr 2019 22:11:30 +0000
ÅAC Microtec subsidiary Clyde Space plans to build and begin operating in 2020 two cubesats equipped with Automatic Identification System (AIS) receivers for Orbcomm in a contract valued at 54 million Swedish Krona ($5.9 million). SpaceNews.com
Tue, 23 Apr 2019 21:20:10 +0000
Iridium CEO Matt Desch said April 23 the company expects to finalize a multi-year renewal of its Enhanced Mobile Satellite Services (EMSS) contract with the Defense Department in the next 30 days. SpaceNews.com
Tue, 23 Apr 2019 16:15:42 +0000
Chinese startup Linkspace succeeded with a vertical takeoff and landing test late last month on the same day fellow private launch firm OneSpace failed to reach orbit with its OS-m rocket. Also that week, two other Chinese companies declared success with engine tests as they push to develop new launch vehicles. SpaceNews.com
Tue, 23 Apr 2019 15:07:50 +0000
Polish space industry startup KP Labs has awarded an order to Scottish cubesat manufacturer Clyde Space which will act as a subcontractor for the company’s Intuition-1 project SpaceNews.com
Tue, 23 Apr 2019 14:30:24 +0000
Relativity announced April 23 it has secured a contract to launch a low Earth orbit satellite for Thai startup mu Space. SpaceNews.com
Tue, 23 Apr 2019 14:00:07 +0000
Colorado Springs was the home of U.S. Space Command from the day it was activated in 1985 until Secretary Rumsfeld reorganized it under Strategic Command in 2002. Today, Colorado Springs remains the epicenter of the U.S. national security space enterprise. SpaceNews.com
Tue, 23 Apr 2019 02:22:43 +0000
After placing more than 60 satellites into orbit on a single Falcon 9 last year, Spaceflight says it will focus on launching smaller numbers of satellites at a time on more launches this year. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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