Latest Space News
Mon, 12 Apr 2021 11:30:17 +0000
The United Arab Emirates doubled the size of its astronaut corps April 10 with the selection of two new astronauts, including the first woman, who will train at NASA starting later this year. SpaceNews
Mon, 12 Apr 2021 08:00:37 +0000
German launch services provider Exolaunch is developing a line of eco-friendly space tugs called Reliant, designed to clean up debris after sending satellites to custom orbits. SpaceNews
Sat, 10 Apr 2021 21:03:13 +0000
NASA announced April 10 it was postponing the first flight attempt of the Ingenuity helicopter on Mars by at least three days after detecting a problem during a final pre-flight test. SpaceNews
Sat, 10 Apr 2021 10:56:08 +0000
DARPA awarded a $22 million contract to General Atomics to design a small nuclear reactor for space propulsion. SpaceNews
Fri, 09 Apr 2021 15:56:04 +0000
The White House released a first look at its budget proposal for fiscal year 2022 that includes an increase in funding for NASA, particularly Earth science and space technology programs. SpaceNews
Fri, 09 Apr 2021 14:05:23 +0000
Japanese camera maker Nikon has acquired a controlling stake in U.S. startup Morf3D, an aerospace supplier that has produced 3D-printed hardware for Boeing satellites and helicopters. SpaceNews
Fri, 09 Apr 2021 11:45:58 +0000
A Soyuz spacecraft carrying two Russian cosmonauts and one American astronaut arrived at the International Space Station April 9, a few hours after its launch from Kazakhstan. SpaceNews
Fri, 09 Apr 2021 00:16:49 +0000
The new chief executive of OneWeb says the company is still pursuing some kind of navigation capability for its broadband satellite constellation, although a full-fledged service may have to wait until a second-generation system. SpaceNews
Thu, 08 Apr 2021 19:40:40 +0000
A new report by ODNI projects that by 2040 China will be the most significant rival to the United States in space, competing on commercial, civil and military fronts. SpaceNews
Thu, 08 Apr 2021 17:31:56 +0000
Rep. Ted Lieu (D-Calif.) hailed the April 8 announcement that Los Angeles Air Force Base will be the permanent home of the U.S. Space Force procurement command.  SpaceNews
Thu, 08 Apr 2021 17:30:56 +0000
The U.S. Space Force is consolidating oversight of space launch activities under a two-star general who will be the deputy commander of Space Systems Command. SpaceNews
Thu, 08 Apr 2021 17:30:08 +0000
The Space Force will re-designate the Space and Missile Systems Center as the headquarters of a new Space Systems Command.   SpaceNews
Thu, 08 Apr 2021 16:30:55 +0000
Phase Four, a startup working on electric propulsion for satellites, has won an Air Force contract to test using an alternative propellant for its thrusters. SpaceNews
Thu, 08 Apr 2021 15:27:36 +0000
Many space startups are not aware of their export control obligations and are exposed to punitive sanctions. With five different export control mechanisms, this is no surprise. If your startup has an international client, supplier, expert, investor, or cooperation, you might just need a permit. SpaceNews
Thu, 08 Apr 2021 14:05:50 +0000
Private equity firm GI Partners plans to buy satellite operator Orbcomm, which specializes in connecting industrial monitoring devices, for about $1.1 billion including net debt. SpaceNews
Thu, 08 Apr 2021 12:49:46 +0000
The coastal cities of Ningbo and Wenchang are planning construction of Chinese commercial spaceports to meet growing demand for launch in China. SpaceNews
Thu, 08 Apr 2021 11:16:08 +0000
The new head of the European Space Agency has outlined his priorities for the next several years, ranging from improving relations with the European Union to increasing commercialization activities. SpaceNews
Wed, 07 Apr 2021 23:29:01 +0000
ULA is still betting on long-endurance upper stages and believes the technology has a bright future.  SpaceNews
Wed, 07 Apr 2021 21:34:51 +0000
SpaceX continued the rollout of its Starlink broadband constellation with another launch of 60 satellites April 7, edging closer to providing continuous global service. SpaceNews
Wed, 07 Apr 2021 14:30:34 +0000
The triumphant landing of the Perseverance rover has inspired all Americans, and indeed much of the world. President Biden should follow it up by launching the program to send humans to Mars. SpaceNews
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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