Latest Space News
Thu, 22 Feb 2018 10:17:21 +0000
A discussion of China at the latest National Space Council meeting took a more nuanced view of the country than is typical in such conversations, seeing the rising space power as a competitor and adversary but also a potential partner. SpaceNews.com
Wed, 21 Feb 2018 23:17:17 +0000
The Army would use small satellites to support tactical imagery needs in the field. SpaceNews.com
Wed, 21 Feb 2018 21:41:25 +0000
Companies that collect data beamed down from small satellites say they expect partnerships and mergers will stem the rising number of new entrants offering ground station services in their market. SpaceNews.com
Wed, 21 Feb 2018 19:46:33 +0000
Vice President Mike Pence and members of the National Space Council approved a series of recommendations Feb. 21 that make modest, and expected, reforms to regulations of commercial space activities. SpaceNews.com
Wed, 21 Feb 2018 17:18:00 +0000
Just as the European masters brought forth a magical period of learning, discovery, invention, fine arts and music 500 years ago, with the advances in the science and technologies proliferating today, we expect a rejuvenation in human space activity in this dawn of the 21st century. SpaceNews.com
Wed, 21 Feb 2018 17:04:37 +0000
For those who have been waiting for the Air Force to shake up its space investment portfolio, the budget request for 2019 was as disruptive as can be expected from the military. SpaceNews.com
Wed, 21 Feb 2018 16:59:51 +0000
The biggest thing since sliced bread might just be a satellite the size of a slice of bread. SpaceNews.com
Wed, 21 Feb 2018 11:23:25 +0000
NASA's vision for lunar exploration includes landing astronauts, from NASA and its partners, on the surface of the moon by the late 2020s, the agency's acting administrator said Feb. 20. SpaceNews.com
Wed, 21 Feb 2018 04:29:31 +0000
In spite of all the safeguards, companies must continually monitor traffic on their global networks to detect attempted or successful penetration and take steps to mitigate the impact of security breaches. SpaceNews.com
Tue, 20 Feb 2018 22:02:12 +0000
Bigelow Aerospace has established a space operations subsidiary whose first task will be to study the market for the company's commercial space stations as it grapples with competition from China and NASA. SpaceNews.com
Tue, 20 Feb 2018 19:50:53 +0000
President Trump's 2019 NASA budget would pull the plug on astronomer's No. 1 priority for the next decade. NASA's former astrophysics chief says Congress should keep WFIRST funded. SpaceNews.com
Tue, 20 Feb 2018 08:57:05 +0000
Vector, one of a growing number of companies developing small launch vehicles, plans to carry out its first orbital launch this summer from Alaska. SpaceNews.com
Mon, 19 Feb 2018 22:29:05 +0000
When members of the National Space Council meet this week, they are expected to discuss, among other issues, regulatory reforms intended to promote growth of the commercial spaceflight industry. SpaceNews.com
Mon, 19 Feb 2018 15:06:38 +0000
What exactly will replace SBIRS remains to be seen. Air Force Secretary Heather Wilson suggested the new system will be “simpler” and more survivable to enemy attacks. SpaceNews.com
Mon, 19 Feb 2018 13:44:31 +0000
Air Force leaders say changes in procurement spending are necessary for the military to ensure air and space supremacy. SpaceNews.com
Mon, 19 Feb 2018 10:38:47 +0000
The head of the organization that manages the national laboratory portion of the International Space Station will leave next month as it deals with an uncertain long-term future for the station. SpaceNews.com
Sun, 18 Feb 2018 15:32:36 +0000
Telesat, with one demonstration satellite for its planned broadband satellite constellation in orbit, expects to announce plans for manufacturing the full system in the coming months as it seeks partners to help fund its development. SpaceNews.com
Fri, 16 Feb 2018 21:45:19 +0000
NASA has certified the current version of the SpaceX Falcon 9 to launch some categories of science missions, a milestone needed for the upcoming, but delayed, launch of an astronomy spacecraft. SpaceNews.com
Fri, 16 Feb 2018 19:38:53 +0000
Eutelsat Chief Executive Officer Rodolphe Belmer is taking a contrary view on short-term capacity leases and the explosive growth of video streaming — two disruptive video trends causing angst among satellite operators with substantial television broadcast business. SpaceNews.com
Fri, 16 Feb 2018 15:20:41 +0000
The U.S. Air Force and Aerojet Rocketdyne are working to revise an agreement to support development of the company's AR1 rocket engine, as questions continue about the engine's long-term future. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
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    Contact information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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