Latest Space News
Thu, 21 Sep 2017 08:38:00 +0100
For the first time in its 19-year history, SMi Group’s Global MilSatCom Conference & Exhibition will be featuring South Korea in its speaker line-up for this year’s event. With recent threats surging within the region, South Korea has instilled urgency in the race to perfect milsatcom systems to ensure overall robust defence capability. Commander of Defence Communication Command, Brigadier General Nag Jung Choi, will be presenting a keynote address on Day 3 of the conference...
Wed, 20 Sep 2017 16:45:00 +0100
In the first act of lunar exploration, Neil Armstrong and Buzz Aldrin were major characters. In setting its sights on the Moon, ESA hopes to bring many more actors to this off-world stage. By testing the market for transport services to the Moon, ESA aims to push the limits of technology and create new models of space business. Touching down on the Moon was a monumental moment in human history. Eight short years and enormous resources took humankind to the lunar surface, initially for le...
Wed, 20 Sep 2017 12:00:00 +0100
Astronomers have used ALMA to capture a strikingly beautiful view of a delicate bubble of expelled material around the exotic red star U Antliae. These observations will help astronomers to better understand how stars evolve during the later stages of their life-cycles. In the faint southern constellation of Antlia (The Air Pump) the careful observer with binoculars will spot a very red star, which varies slightly in brightness from week to week. This very unusual star is called U Antliae and...
Wed, 20 Sep 2017 11:03:00 +0100
SES, EchoStar Corp., and Airbus Defence and Space announced today that the new EchoStar 105/SES-11 spacecraft, built by Airbus, has been shipped from the Airbus facilities in Toulouse, France, to Cape Canaveral, Florida, for its forthcoming launch by SpaceX in October. The first satellite that EchoStar has constructed with manufacturer Airbus, EchoStar 105/SES-11 will be launched by SpaceX on a flight-proven Falcon 9 rocket from Launch Complex 39A at Kennedy Space Center, Florida. EchoStar 10...
Tue, 19 Sep 2017 19:30:00 +0100
Today Lockheed Martin (NYSE: LMT) debuted a new family of satellite buses that form the core of nearly every space mission. From nanosats to high-powered satellites, the versatile lineup incorporates dozens of major enhancements and hundreds of common components that speed production and reduce cost. The company announced the lineup at the Air Force Association Air, Space & Cyber Conference. "We've invested $300 million in revamping our satellite solutions from top to bottom, applying what we...
Tue, 19 Sep 2017 15:54:00 +0100
FLYHT Aerospace Solutions Ltd. (TSX VENTURE: FLY) (OTCQX: FLYLF) (the "Company" or "FLYHT") is pleased to announce a flight trial with Inmarsat, and would like to bring attention to an Inmarsat press release titled Inmarsat to demonstrate advanced SwiftBroadband-Safety capabilities in flight trial with FLYHT on September 19, 2017. This trial will demonstrate the use of FLYHT's Automated Flight Information Reporting System (AFIRS(tm)) to send data to the UpTime(tm) Cloud management platform via I...
Tue, 19 Sep 2017 14:53:00 +0100
With the ''Space Strategy for Europe'' from the European Commission and the new ESA roadmap on the table, the European space stakeholders will have the great opportunity to debate and influence, at the highest level, the medium and long term development of European space programmes and of the spread of space services in many economic and societal activities as well as in a wide range of public fields, including security and defence. Download Conference Agenda | Register to a...
Tue, 19 Sep 2017 14:00:00 +0100
Kratos Defense & Security Solutions, Inc. (NASDAQ:KTOS), a leading National Security Solutions provider, announced today that it has recently received approximately $8.2 million in orders or specialized products in support of satellite global positioning system protection and communication systems. Work on these recent orders will be performed in secure Kratos manufacturing facilities. Due to customer related, competitive and other considerations, no additional information will be provided rel...
Tue, 19 Sep 2017 11:51:00 +0100
The Sun's recent activity has caught the interest of scientists and space weather forecasters worldwide, highlighting the need to keep a watchful eye on our star and its awesome power. On 6 and 10 September, our Sun produced a pair of solar flares, the strongest observed in over 10 years. They were accompanied by huge eruptions of billions of tonnes of matter into space. While many such eruptions fall back onto the hot surface, these two did not and became 'coronal mass ejections' (CMEs) -...
Tue, 19 Sep 2017 08:19:00 +0100
NASA's Hubble Space Telescope has observed a planet outside our solar system that looks as black as fresh asphalt because it eats light rather than reflecting it back into space. This light-eating prowess is due to the planet's unique capability to trap at least 94 percent of the visible starlight falling into its atmosphere. The oddball exoplanet, called WASP-12b, is one of a class of so-called "hot Jupiters," gigantic, gaseous planets that orbit very close to their host ...
Fri, 15 Sep 2017 18:13:00 +0100
Raytheon Company (NYSE: RTN) will continue its support for NOAA's Advanced Weather Interactive Processing System program that ingests and analyzes weather data, creating useful visualizations for forecasters and distributing time-sensitive weather statements such as watches and warnings across the United States. Used by more than 140 National Weather Service field offices, the AWIPS program informs decisions that save lives and protect property during natural disasters. Under the $269 mill...
Fri, 15 Sep 2017 15:00:00 +0100
The international Cassini mission has concluded its remarkable exploration of the Saturnian system in spectacular style, by plunging into the gas planet's atmosphere. Confirmation of the end of mission arrived at NASA's Jet Propulsion Laboratory at 11:55 GMT/13:55 CEST with the loss of the spacecraft's signal having occurred 83 minutes earlier at Saturn, some 1.4 billion km from Earth. With the rocket propellant for manoeuvering the spacecraft fully expended as planned touring Saturn and i...
Fri, 15 Sep 2017 14:17:00 +0100
Four of the latest set of Galileo navigation satellites will be launched on Ariane 6 rockets - ESA's first contract to use Europe's new vehicle. The launches are scheduled between the end of 2020 and mid-2021, using two Ariane 62 rockets - the configuration of Europe's next-generation launch vehicle that is best suited to haul the two 750 kg navigation satellites into their orbits at 23 222 km altitude. Under development, Ariane 6 is Europe's newest launcher, designed to extend guaranteed ...
Fri, 15 Sep 2017 14:00:00 +0100
The Space Alliance, formed by Thales Alenia Space (Thales 67%, Leonardo 33%) and Telespazio (Leonardo 67%, Thales 33%), today signed a partnership with the US-based company Spaceflight Industries which includes the following elements: A minority investment in Spaceflight Industries, which through its BlackSky business, has developed a geospatial platform and plans to build and operate a constellation of 60 small high-resolution observation satellites featuring very short revisit times; ...
Tue, 12 Sep 2017 16:33:00 +0100
Lockheed Martin (LM) unveiled a new small unmanned aircraft system (UAS) that has been designed and developed in the UK at the Defence and Security Equipment International (DSEI). OUTRIDER is a lightweight, canister launched UAS that has been designed by engineers at Lockheed Martin UK's Havant facility in partnership with Wirth Research, an engineering company with specialisation in aerodynamics and composite materials. At only four inches wide and weighing only 1.7 kilograms, it is designed...
Mon, 11 Sep 2017 13:00:00 +0100
Orbital ATK, a global leader in aerospace and defense technologies, today announced significant progress on the industry's first commercial in-space satellite servicing system. The Mission Extension Vehicle-1 (MEV-1) spacecraft successfully completed its critical design review earlier this year and is now in production with about 75% of the platform and payload components already delivered to the company's Satellite Manufacturing Facility in Virginia. The spacecraft will begin system-level testi...
Mon, 11 Sep 2017 10:07:00 +0100
Boeing will design and build seven super-powered medium earth orbit (MEO) satellites for SES, delivering efficient high-performance data communications services to users around the world. The O3b mPOWER satellites will include Boeing's most-advanced digital payload technology and will be built using electronics from the flight-proven 702 satellite platform customized to support the unique MEO environment. "With this new technology and design, Boeing is able to build satellites faster and m...
Wed, 6 Sep 2017 16:31:00 +0100
EchoStar Corporation and Lockheed Martin announced today that the EchoStar III satellite has been successfully recovered following an anomaly that occurred in late July and retired per the FCC regulations. "After the initial loss of contact, with a joint effort by EchoStar and Lockheed Martin, a command and control link was reestablished and deorbit maneuvers performed" said Derek de Bastos, chief technology officer for EchoStar Satellite Services L.L.C. "EchoStar III is now safely in a grave...
Wed, 6 Sep 2017 15:24:00 +0100
Orbital ATK, a global leader in aerospace and defense technologies, recently completed an important qualification test of the avionics system for the solid rocket boosters the company has developed and is now manufacturing for NASA's Space Launch System (SLS). Completion of this milestone is an important step toward preparing the SLS and Orion spacecraft for their first flight in 2019. Two Orbital ATK-developed five-segment rocket boosters will be used on each SLS launch to help provide initial ...
Tue, 5 Sep 2017 14:07:00 +0100
Launch is the most strenuous part of a satellite's life. To survive the extreme sound wave pressure and pounding vibrations generated by more than 700,000 lbs. of thundering rocket thrust, spacecraft need a solid, reliable design if they hope to arrive operational on orbit. On July 13, Lockheed Martin (LMT)'s second, fully-assembled GPS III space vehicle (SV) completed a realistic simulation of its future launch experience and passed this critical acoustic environmental test with flying color...
More space news...
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  • CV: Design engineer

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    Personal information
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:30-03-2017 (06:16)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Jun/2016 - Now ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Now Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html2012 Personal productivity and management (4 hours) at Fundaci ́on tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

    Skills

     

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: L A TEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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