Latest Space News
Sat, 20 Oct 2018 04:15:10 +0000
A Mercury-bound science mission from the European and Japanese space agencies began a seven-year journey to the Solar System’s smallest planet Oct. 19 aboard and Ariane 5 rocket. SpaceNews.com
Fri, 19 Oct 2018 22:06:59 +0000
Vector, one of dozens of ventures developing small launch vehicles to serve perceived high demand for small satellite launches, announced Oct. 19 that it closed a $70 million Series B round to move into full operations. SpaceNews.com
Fri, 19 Oct 2018 19:41:19 +0000
Three regional satellite operators with C-band coverage over the United States have complained to U.S. telecom regulators about being left out of a group led by four of the world’s largest satellite operators to arrange a proposed spectrum transfer to the wireless industry. SpaceNews.com
Fri, 19 Oct 2018 18:20:52 +0000
Thornberry's letter to DoD: "It is important for us to understand the benefits and challenges of a full range of options.” SpaceNews.com
Fri, 19 Oct 2018 16:45:34 +0000
François Lombard, who took the helm at Airbus Intelligence in early 2017, is encouraging this type of innovation and partnerships like the ones formed recently with Earth observation constellation operator Planet and Orbital Insight, a geospatial analytics company. SpaceNews.com
Fri, 19 Oct 2018 00:50:39 +0000
As NASA evaluates proposals for commercially developed small lunar landers, the agency is now seeking payloads that could fly on those spacecraft despite concerns from some scientists that they don’t know if their experiments are compatible with those landers. SpaceNews.com
Thu, 18 Oct 2018 17:00:25 +0000
The last mission needed to complete Iridium Communications’ second-generation satellite constellation is scheduled for Dec. 30, Iridium CEO Matt Desch said today. SpaceNews.com
Thu, 18 Oct 2018 08:26:14 +0000
SMM Hamburg, the biennial international maritime conference in Germany Sept. 4-7, attracted not only shipbuilders but also satellite operators eager to offer global communications for autonomous vessels. SpaceNews.com
Wed, 17 Oct 2018 21:44:31 +0000
Between now and when the the Air Force starts buying launch services from new competitors, ULA and SpaceX will be competing “one mission at a time.” SpaceNews.com
Wed, 17 Oct 2018 19:23:01 +0000
To connect the masses, megaconstellations will need mega antennas mega cheap. Antenna makers need mega orders to make that happen. SpaceNews.com
Wed, 17 Oct 2018 19:11:40 +0000
Intelsat invested in Africa Mobile Networks (AMN), a U.K.-headquartered group of companies with telecom infrastructure in Africa, to reach "ultra-rural" parts of the sub-Saharan side of the continent. SpaceNews.com
Wed, 17 Oct 2018 18:37:44 +0000
As the Pentagon moves to stand up a U.S. Space Command and Congress debates whether it makes sense to create a Space Force, a central focus is to defend satellites from orbital weapons that would seek to damage or destroy U.S. assets in space. SpaceNews.com
Wed, 17 Oct 2018 15:27:27 +0000
Small launch vehicle company Rocket Lab announced Oct. 17 that it will build its second launch pad, and first in the United States, at Wallops Island in Virginia. SpaceNews.com
Wed, 17 Oct 2018 07:58:08 +0000
This was ULA’s eighth launch this year, the 131st since the company was formed in 2006, and will be its 50th launch for the U.S. Air Force. SpaceNews.com
Tue, 16 Oct 2018 22:57:26 +0000
A Swedish company with plans for a geostationary communications satellite announced Oct. 16 a contract with SpaceX for a Falcon Heavy launch no earlier than the fourth quarter of 2020. SpaceNews.com
Tue, 16 Oct 2018 20:52:46 +0000
The NASA astronaut who was on the aborted Soyuz mission to the International Space Station says he has “complete confidence” in the Russians despite this launch failure and other problems and looks forward to flying again on the spacecraft. SpaceNews.com
Tue, 16 Oct 2018 19:37:17 +0000
For all the enthusiasm about lunar exploration, and announcements made during the conference, there were far fewer specific details about just how to achieve those goals. SpaceNews.com
Tue, 16 Oct 2018 18:26:57 +0000
ThinKom’s recent collaborations with satellite operators Telesat and SES have the antenna builder jockeying to compete with Viasat, IsoTropic Systems and others in the race to build affordable high-tech antennas that can link with satellite constellations in non-geosynchronous orbits. SpaceNews.com
Mon, 15 Oct 2018 23:40:09 +0000
45th Space Wing Commander Brig. Gen. Schiess: Gen. Raymond “is pushing us to look at ways to be more responsive.” SpaceNews.com
Mon, 15 Oct 2018 23:06:02 +0000
Paul Allen, the billionaire co-founder of Microsoft who backed the winning entry in a suborbital spaceflight competition and later funded development of a massive air-launch system, passed away Oct. 15. SpaceNews.com
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  • CV: Design engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
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    Candidate Profile
     Date Submitted:22-01-2014
     Last Modified:13-10-2018 (08:39)
    Job information
     Current job:Design engineer
     Employment Term:Either
     Job location:Europe only
     Date available:>3months
     Industry:
     KeywordsSystemC C++ Artificial Intelligence Verilog FPGA Linux
    CV

    Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.

     

    Experience

    Apr/2018 - Now Apple, http://www.apple.com
    Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
    Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog

    Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
    Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
    Jun/2016 - Mar/2018 Design engineer
    • Design and verification (System Verilog and UVM) for DC-DC controller
    • Responsible of communication interfaces: SPI, I2C
    • Responsible of design checks: lint, CDC

     

    Sep/2015 - Jun/2016 Intel, http://www.intel.com

    Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.

    Sep/2015 - Jun/2016 System modelling consultant
    • SystemC simulation specification and development with Intel CoFluent
    • Scoreboard responsible and develop C++ scoreboard classes
    • Responsible of test launching scripts and result analysis

     

    Aug/2010 - Jul/2015 Marvell, http://www.marvell.com

    Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.

    Mar/2015 - Jul/2015 ASIC engineer

    • Member of tape-out sub-project team

    • Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners

    • Clock maximum transition time fix with Synopsys ICC

    • Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations

    • Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows

    • Responsible of check-list for ASIC tape-out

    Jul/2011 - Jul/2015 FPGA engineer

    • Responsible of FPGA prototyping sub-project

    • Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE

    • FPGA platform analysis and selection

    • Prototype clock architecture with System Verilog:

    – Specify clock architecture for: reuse, easy changes, aligned clocks between

    FPGA

    – Generate RTL generic modules for clock generation and buffering

    – Generate the RTL of clock architecture: generation, multiplexing and buffering

    • Prototype reset architecture with System Verilog:

    – Specify reset architecture for reuse existing reset synchronization RTL Verilog modules

    – Group clock reset instances for FPGA partitioning

    – Generate the RTL for global reset generation and reset for each clock

    • Prototype IO ring with System Verilog:

    – Specify generic IO modules for: reuse, easy changes and instantiating

    – Generate RTL generic modules for IO

    – Generate RTL IO-ring grouping clocks by functionality

    • Check the RTL with chip level simulation (ncverilog)

    • FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA

    • Select board resources and connections between FPGA and external interfaces

    • Implementation of FPGA: check the implementation results, modify the design and fix the resource locations

    • Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start

    • This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )

    Aug/2010 - Jul/2011 Senior digital design engineer

    • Member of ASIC DFT sub-project team

    • ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion

    • ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code

    • This was developed once, and the scripts reused for the following projects

    • Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa

    • Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST

    • Checked with different chip level simulations (ncverilog) equivalent to ATE runs

     

    Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es

    Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).

    It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.

    2009 - Aug/2010 Senior design engineer

    • Member of digital ASIC development team

    • Specification, development and verification of HW blocks with System Verilog

    • Based in: generic TLM interfaces, use of types, structures and classes

    • Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation

    • Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)

    • PLC sub-system (PLC transmission frame generation): design and RTL coding

    – Division and specification using generic blocks and interfaces

    – Main parts: control, frame calculation and a pipeline for DMA request and frame generation

    – Auxiliary queue managers for data consistence

    • Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification

    • Development of golden model for the verification

    2007 - 2009 System modelling engineer

    • Member of design flow improvement team

    • Development of high abstraction level environment with SystemC and TLM

    • Specification, development and support of simulation environment

    • Define TLM communication interfaces and develop the related generic classes

    • Define and development of generic blocks

    • Technical follow-up of share project with “Universidad de Cantabria”

    Jun/2001 - 2007 Design engineer

    • Member of digital ASIC development team

    • Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog

    • Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates

    • Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)

    Nov/2000 - Jun/2001 Student in practice (end of studies project)

    • Development connection between commercial IP (for PCI bus) and proprietary design with Verilog

    • Clock cross domain

     

    Studies

    2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com

    2017 UVM adopter class (32h), http://www.doulos.com

    2016 System Verilog for verification specialists (24h), http://www.doulos.com

    2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org

    2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html

    2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena

    2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach

    1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es

     

    Skills

    • Computer languages

    – Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL

    – Programming: C, FORTRAN, Pascal

    – Object oriented programming: C++, Delphi, Java

    – Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot

    – Planning: CLIPS/COOL, PDDL

    • Tools

    – FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms

    – FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE

    – ASIC synthesis: design-compiler (Synopsys)

    – ASIC back-end: prime-time (Synopsys), ICC (Synopsys)

    – HDL simulation: ncverilog (Cadence)

    – Debug: ddd, multimeter, oscilloscope, logic analyzer

    – Lint (for Verilog): spyglass (Attrenta)

    – System modelling: CoFluent (Intel)

    – Other integrated environments (IDE): repast, SNNS, octave

    • Working environment

    – Operating system: Linux

    – Version control: cvs, git

    – Documents and office software: LATEX, office, open office

    • Languages

    – English: B2

    – Spanish: native

    – Catalan: native

     


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