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CV: CMOS device model engineer
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Profile
A highly motivated Masters degree qualified electronics and IC development engineer with a conscientious, solutions-oriented work ethic.
Proven as a reliable, supportive and respectful team player, with a resourceful and proactive attitude in autonomous roles.
Experience in delivering robust solutions from a rigorous and efficient lateral perspective.
Experience
‣ General: Power and Energy aware nano-scale A/MS and RF CMOS IC development
‣ Specific: Design analysis, design optimization, behavioural modelling, verification
‣ Recent: CMOS analogue device modelling for Space and Nuclear ASIC applications
‣ RF: Transceiver models and circuit design for IC simulation methodology vehicles
‣ Analogue: Band-gap, Op-amp, XTAL oscillator design, frequency synthesis models
‣ Mixed-Signal: Σ-Δmodulator, data converter, PLL, CDR, PHY Tx/Rx IC modeling
‣ Digital: Basic exposure to RTL, SystemVerilog, and ASIC design flow processes
‣ Semiconductors: DSM CMOS, FD-SOI CMOS, RF-CMOS, BiCMOS, SiGe, Bipolar
‣ EDA: Cadence SKILL, Verilog-AMS, SpectreRF, Mentor Eldo, Calibre, Questa-ADMS
‣ ICT: Perl, Matlab, Python, UNIX/Linux Shell, C, Tcl-Tk, Windows 8 MS Office tools
Achievements
‣ MOS ELT device development to facilitate design of ASICs for Space applications.
‣ Created auto-regression bench methodology, facilitated rapid PHY IP verification.
‣ Developed SoC power management analysis tools, enhanced PI design efficiency.
‣ Designed 32MHz XTAL Oscillator in 180nm CMOS for automotive wireless sensor.
‣ Modelled and verified QAM and DVB-s2 TV tuner blocks to spec., and IC tape-out.
Consultancy
2014-2015 IMEC, Leuven, Belgium:
Analogue Device Modelling - 180nm CMOS
Spice BSIM3V3 and RHBD characterisation of full-custom ASIC library MOS ELT device Spice models targeted to space applications.
Parameter extraction and characterization of devices exposed to ionizing radiation.
2013-2014 Infineon, Munich, Germany:
AMS Verification Flow Methodology
Conceived mixed-signal verification plan for digitally assisted voltage regulator.
2012-2013 Intel Mobile, Munich, Germany:
Analogue IP bench - 28nm CMOS
Created analogue ADE-XL auto-regression bench in SKILL, Verilog-A, and Matlab.
Verified M-PHY 28nm CMOS Transceiver IP to MIPI Spec.
2010-2012 ST-Microelectronics, Crolles, France:
AMS - 28nm FDSOI CMOS
Power Integrity analysis and custom PI tools development for ARM A9 2.3GHz MPU.
Modelled Dual Core SoC, DPLL power management interface and embedded analogue switch with SiP, SMPS, PCB trace scenarios.
2010-2010 SensorDynamics, Graz, Austria:
Analog IC Design - 180nm CMOS
32MHz crystal oscillator IC design for automotive wireless sensor IP.
2008-2009 Intel Corp., Swindon, UK:
TV Tuner IC Verification - 65nm CMOS
Analog/Digital HDL Verilog-AMS sub-system modelling of Σ-ΔMASH PLL Synthesiser, DCO, base-band VGA, AGC, CT/DT filters,
SAR A/D converter for QAM and DVB-S2 Tuner IC verification. Aligned with RF and Digital demodulator IC group activities.
Permanent
2008-2008 Adaptalog Ltd., Cambridgeshire, UK.
Analogue IC & Systems Design Engineer
+Developed 0.6μBiCMOS sub-circuits in SIMetrix Micron A-D and ICED (X-FAB PDK) for low noise band-gap and TCXO IC design.
2005-2008 Philips/NXP Semiconductors, Nijmegen, The Netherlands.
RF IC Design Technology Engineer: WiFi, Bluetooth, CMOS
+Provided ‘super-user’RF simulation consultancy for Bluetooth IC design.
+RF-AMS IC design methodology and successful EDA workshop deliveries.
+Deployed RFIC tools and flow support in Benelux, France and Germany.
2000-2004 Sony Semiconductor Europe, Basingstoke, UK.
IC Design Methodology & EDA Engineer: DVB-H, WCDMA, BiCMOS
+Developed OCEAN regression bench and verified XTAL oscillator to spec.
+Designed OTA, band-gap ref., 8-bit flash ADC and standard logic cells.
+Developed worst-case corner simulation bench IP re-use methodology.
1998-2000 Ultra Electronics Controls Division, London, UK.
Avionics Hardware Engineer: Airbus LGCIU Sensor/Controls
+Landing gear position/proximity sensor controls test and development.
+Diagnosed and resolved chronic CPU motherboard failure mechanisms.
1996-1997 Panasonic (Matsushita Avionics Systems Corp.), Slough, UK.
Avionics/Electronics Engineer: In-flight entertainment systems
+Contributed heavily to repair turn-around progress in excess of 25%.
1992-1995 Tameside General Hospital, Greater Manchester, UK.
Medical Electronics Technician Engineer: Neonatal Criticare
+Optical, Ultrasound, and Piezo sensor metrology, repair and calibration.
+Developed PPM database for ISO 9001(BS EN ISO 13485) accreditation.
Training
2006 EPFL, Lausanne, Switzerland.
RFIC Design- Electronics Laboratories Advanced Engineering
2006 University of Manchester, Manchester, UK.
MSc Low Power Systems Integration- modules
CEESI distinction ARM SoC Design, Mixed-Signal IC design
2003 Imperial College, London, UK.
CMOS Analogue IC Design- Continuing Professional Development
1997-1999 Brunel University, Uxbridge, West London, UK.
MScMicroelectronics Systems Design
Dissertation: High-Performance PLL IC Design
1995-96 University of Hertfordshire, Hatfield, Herts, UK.
Post-Grad. Certificate Optoelectronics Systems
Memberships
2015 Institute of Electrical and Electronic Engineers - IEEE
Interests
Philosophy, science, technology, current affairs, history, art, music, and martial sports.
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