· 2011-2014 : Graduate in Embedded Systems at ESIGELEC, Engineering school (Rouen, France)
· 2009-2011: Three-year intensive program preparing for the national competitive exam for entry in engineering schools (La Rochelle, France)
· 2006-2008 : Baccalaureate (A-level equivalent), specialized in electricity, with honours (Angoulême, France)
· English : TOEIC 920
· 5 Keywords : FPGA, VHDL, SystemOnChip, Microsemi, Modelsim
2016-now FPGA Engineer at Microcameras Space and Exploration
Main activities executed:
• FPGA Requirements definition based on the customer system requirements.
• Data handling ICD definition based on SpaceWire and Packet Utilization Service (PUS).
• RTL and testbench/BFM in VHDL, simulation (VUnit framework and ModelSim), synthesis (Synopsys Synplify Pro), place & route (including
SDC definition, static timing analysis, post‐layout simulation), debug on target (Synopsys Identify).
• Complete redaction of the datapack documentation for all majors milestones (SRR, PDR, CDR).
• BepiColombo (ESA): Final implementation and bug fixing of a camera controller unit (CCU) with its associated cameras. Development of
the EGSE and a camera simulator.
• JMC (ESA): Complete FPGA development of the JUICE Monitoring Camera, based on a RT‐AX FPGA and a rolling shutter image sensor.
• MCA (ESA): Responsible for the FPGA development of the BIOMASS Monitoring Camera, based on a global shutter image sensor.
• VIS (NASA): In a team of three, responsible for the FPGA development of the VIPER Visible Imaging System used for navigation based on 2
CCUs and 8 cameras. The CCU design is using AXI‐Stream and is connected to several memories (NAND Flash/SDRAM/MRAM)
• Set up the FPGA environment (Git, automated regression testing for simulation (docker based), automated code‐coverage extraction).
2015 - 5 months (Consultant) Subcontractor for the CNES – RPW instrument:
Complete analysis of 6 FPGAs on documentations, source code, simulation, place and route and tests on targets to help the laboratories bring their FPGAs to maturity or correcting detected bugs. CodeCoverage, static timing analysis of interfaces and set of adequate timing constraints. Use of RTAX and RT54SX FPGAs, SystemOnChip (LEON3FT), GAISLER’s Ips, SpaceWire, AMBA (AHB, APB)
2014-2015 - 2 months (Consultant) Subcontractor for SAGEM, France:
· Writing of around 80 specifications
· Development in VHDL of the synchronisation video module for 5 channels
· Development in C for the NIOS SystemOnChip interfacing the FPGA with a flash memory storing the informations
· Simulation with Modelsim and test on target (Altera Cyclone V)
2014 - 2 months (Consultant) Subcontractor for TECHNOFAN (SAFRAN), France : Modification of an old test environnement in order to adapt it to a new FPGA. I developped and adapted 9 emulators (SPI, open and closed-loop controller...) to stimulate all the functionalities of the FPGA. The test environnement is automated, it reads commands from text files and generates reports.
2014- 6 months (Internship) 1553 bus, ALTRAN, France : Evaluation of a commercial MIL-STD-1553 IP for a future implementation in a Microsemi FPGA.
· Writing of encoder/decoder specification applied to 1553 protocol (Manchester II encoding)
· Development of the encoder/decoder, unitary testbenches and system testbench using VHDL
2013 -3 months (Internship) Pulse Oximetry, Nanjing, China : Design of a PCB using « Altium Designer ». The tasks done during this internship are the following :
· Choice of composants
· Designing the circuit
· Place and Route
Tools: Libero Project, Microsemi Designer, Quartus II, QSYS, Altium Designer, SVN, ModelSim, ActiveHDL, Xilinx ISE Project Navigator, IAR Embedded Workbench, Code Composer Studio, Codeblocks, gcc, MATLAB, LABVIEW, Eclipse, Microsoft Word & Excel, Keil µVision
Programming language: VHDL, C, TCL, HTML, PHP, Java
OS :Windows, Linux, MicroC/OS-II
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