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CV: Research Associate
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Research Associate at DIAT DRDO Pune
Research
Interests
Space System Modeling and Veri cation, Signal Processing for Communications, Digital
Telemetry Schemes for Deep Space Communication and Control Systems.
Education
1) Indian Institute of Technology, Roorkee, Uttarakhand
M.Tech., Electrical Engineering, Major: June 2012
Dissertation Topic: Digital Implementation of Radio Frequency Digital Receiver
based on Field Programmable Gate Array (FPGA)
Advisors: Dr. (Ms.) Indra Gupta, Ph.D and Dr. Vishal Saxena, Ph.D
2) Rajiv Gandhi Technical University, Bhopal, MP
B.E. Electronics and Communication , June 2010
Major Project: Advance Satellite Communication System
Advisors: Ms. Nitu Singh (Assistant Professor) and Mr. Sanjay Mishra (Associate
Professor)
Research
Experience
1. Research Associate August 2013 to present
Sensor Data Analysis Laboratory
Defence Institute of Advanced Technology, DRDO
Supervisor: Dr. Chinmoy Bhattacharya, Sc 'G' , Ph.D
(a) Project : Real Time SAR image generation algorithm using CUDA platform.
Contribution :
Implementation of Singular Value Decomposition method for parallel
processing.
Developed an algorithm for SAR image generation from RADARSAT-1
raw signal data which inherently executes parallelism for matched ltering
of block data vectors.
Processing of the input raw video data in range dimension followed by
processing the range image processed data in the azimuth dimension.
Detailed analysis of speed performance in radar lter.
Extensive radar data analysis.
(b) Project : Technology demonstrator for very light FM-CW SAR.
Contribution :
FM-CW SAR signal model.
Development of SAR processing algorithms, i.e. Range Doppler algorithm,
SPECAN, Chirp Scaling algorithm.
Ground and slant range calibration of radar hardware using corner re ectors
in di erent environments (Anechoic chamber and open ground).
Design of RailSAR testbed for imaging from building rooftop.
(c) Project: Design and Implementation of Transmitter for Airborne Platform
on FPGA using LabVIEW. (ADA Bangalore).
Contribution :
Design algorithm using LabVIEW on NI PXI chassis.
Mathematical computation for on board time sync with data rate.
A novel approach of single cycle timing loop implementation for parallel
processes.
Design principles have been verifed with standard COTS receiver.
(d) Project: Implementation and Calibration of robust receiver for CPM based
signals.
Contribution :
Simulation of DDC using LabVIEW on NI PXI chassis.
Simulation of DDS for L and S band.
Implementation of the reciever is yet to done on PXI chassis.
2. Post Graduation Research July 2010 to 2012
Microprocessor and Sensor Data Laboratory
Indian Institute of Technology, Roorkee
Supervisor: Dr. (Ms.) Indra Gupta, Associate Professor, EED
(a) Project : Digital Implementation of RF Digital Receiver on FPGA.
Contribution :
Simulation of RF receiver on MATLAB.
RF signal parallel Digital Down Converter with frequency domain Correlation
Processing.
Reduced the analog deviation primarly with higher performance than that
of normal receivers.
(b) Project : Real time implementation of ADC-DAC interfacing using MATLAB
SIMULINK on DSP kit.
Contribution :
Successfully Interfaced ADC-DAC to DSP kit.
3. Under Graduation Research July 2006 to 2010
Electronics and Communication Laboratory
Rajiv Gandhi Technology University, Bhopal
Supervisor: Prof. Sanjay Mishra and Nitu Singh, Asstitant Professor, EC
(a) Project : Advance Satellite Communication Systems.(Major Project)
Contribution :
Simulation of the design on MATLAB.
Power budget computation for the entire design.
Study of design intricacies for hardware implementation.
(b) Project : Pulse Width Modulator generator design using 4 Mhz crystal
oscillator and maximum permissible pulse width of 250 ms (Minor Project).
Contribution :
Implemented the design using PIC microcontroller.
Accepted
Conference
Paper
1. Chaubey, Gorakh Nath, Hendre, Aniket. and Bhattacharya C. ,"Design of
Recon gurable Shaped O set Quadrature Phase Shift Keying (SOQPSK) Transmitter
on Field Programmable Gate Array (FPGA)" 2015. Submitted to IEEE TSP
2015, Prague Czech Republic.
Journal in
Preparation
1. Chaubey, Gorakh Nath and Bhattacharya, C. , "Implementation of bandwidth
ecient digital modulation on FPGA platform for airborne telemetry."
Hardware and
Software
Skillls
NI PXI Chassis, Vector Network Analyzer, Spectrum Analyzer
Matlab, LabVIEW, VHDL, C, C++, Python, MikTeX (Latex)
Presentations
Design Veri cation of CPM based SOQPSK-TG Transmitter and FMCW SAR trails.
Integrated Test Range, Chandipur, Orissa Sep 2014
Air Trails for FMCW-SAR, Ahmednagar, Maharastra July 2014
Indian Institute of Technology
Digital Control Systems and FPGA training sessions Nov 2011
Avionics, Mechatronics and Robotics Apr 2011
Teaching &
Consulting
Experience
Assistant Professor August 2012 -2013
Control Systems, Electromagnetic Theory, Analog Electronics, Antenna and wave
propagation and Analog Communication
Electronics Department
IEC - CET Greater Noida
Miscellaneous
Secured 99.89 percentile in Graduate Aptitude Test in Engineering March 2010.
Member of Student A airs Council July 2011 - July 2012
Mess Secretary (Govind Bhawan, IIT Roorkee) August 2011- June 2012
Assisted to manage event ARPAN. March 2012
References
Dr. Chinmoy Bhattacharya, PhD
Armament Research and Development Establishment E-mail: cbhat0(at)ieee.org
Defence Research and Development Organisation.
Dr. Bharat. B. Kale , PhD
Director, Scientist-F
Centre For Materials For Electronics Technology E-mail: kbbb1(at)yahoo.com
Government of India
Dr. Kumar Digvijay Mishra, PhD
Professor
Controls, Mechatronics, and Robotics E-mail: kumardigvijaymishra(at)yahoo.co.uk
DIAT DRDO
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