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Wed, 05 Aug 2020 15:00:14 +0000
Commercial satellite operatorSES has selected SpaceX and United Launch Alliance to each launch two geostationary satellites designed to replace C-band capacity in the United States that the Federal Communications Commission is repurposing for 5G cellular networks.  SpaceNews
Wed, 05 Aug 2020 14:21:35 +0000
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The NASA astronauts who flew on the SpaceX Demo-2 commercial crew vehicle said they were pleasantly surprised at how well the Crew Dragon spacecraft performed. SpaceNews
Wed, 05 Aug 2020 10:17:39 +0000
After months of delays and testing setbacks, a prototype of SpaceX’s Starship next-generation reusable launch vehicle made a brief “hop” flight Aug. 4 at the company’s South Texas test site. SpaceNews
Wed, 05 Aug 2020 08:24:24 +0000
China is advancing the development of the Chang'e-7 lunar south pole mission and a complex campaign to study comets and return samples from a near-Earth asteroid with a single orbiter. SpaceNews
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  • CV: Digital / FPGA Engineer

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    Personal information
     Name:<withheld>
     Age:<withheld>
     Country:<withheld>
     Location:<withheld>
    Contact information
     Email:<withheld>
     Phone:<withheld>
     Mobile:<withheld>
    Candidate Profile
     Date Submitted:05-10-2015
     Last Modified:05-10-2015 (07:19)
    Job information
     Current job:Digital / FPGA Engineer
     Employment Term:Permanent
     Job location:Europe only
     Date available:within a month
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Consulting/Engineering Services
     Keywordsfpga
    CV


     

    Leiden, Netherlands

     

     

     

    Date of birth 14/12/1981 | Nationality Spanish    

     

    Background

    Telecommunications Engineer with more than seven years experience in systems and microelectronic designs. Good knowledge of the space environment and its effects on components and systems, low level communication protocols, digital processing and analog design.

     

    Work Experience

    05/2013 – Present

    Senior Hardware Engineer

     

    SSBV – Noordwijk, Netherlands

     

    w Defining requirements and specifications between systems & sub-systems

    w Performing and providing technical support on digital developments and proposals

    w Defining architecture and resource estimation on sub-systems and FPGAs

    w Coordinating Firmware team activities

    w Defining PA and designing flows

    w Work with:

    § SpaceWire Node, Router, RMAP and SpaceFibre

    § Defined and designed a new high-speed communication protocol base on WizardLink

    § Designed a new On-Board Computer for Space application such as SARadar

    § Defined a new generation of SARadar instruments

     

    08/2011 – 12/2012

    Microelectronic Engineer

     

    Arquimea Ingeniería – Madrid, Spain

    Configurable mixed-signal ASIC for Cosmic Vision instrumentation payload (in Medium frequencies 100k~10M; and High frequencies 10M~100M). The ASIC contains a set of blocks that can be individually configured through the configuration interface so the ASIC can be used for different applications. These configurable blocks are: ADC, DAC, DC DAC, LNA, Power Amplifier and Filter

    w Designing ASIC of mixed signal

    w Performing and providing technical direction for FPGA developments and proposals

    w Leading small groups of people

    w Supervising junior engineers and coordinating project tasks and milestones

    w Complete FPGA development including specification, design, verification and synthesis

    w Work with:

    § Designed analog circuits for a configurable mixed signal ASIC (ADC, DAC, PA)

    § Designed an FPGA used for identifying SEEs on a chip under qualification(radiation)

     

    10/2010 – 08/2011

    FPGA Manager

     

    Airbus Defence & Space, Crisa – Madrid, Spain

     

    wDefining high level requirements and architecture

    wSupervising junior designers and coordinating project tasks and milestones

     

    08/2008 – 08/2011

    FPGA Engineer

     

    Airbus Defence & Space, Crisa – Madrid, Spain

     

    w Complete FPGA development including specification, design, verification and synthesis

    w Coordinating project tasks and milestones

    w Interfacing external customers, providing technical documentation

    w Work with:

    § Designed of an FPGA to cipher TM packets (Band-S) in real-time using AES algorithm

    § Designed of an FPGA in charge of TM, UART and control of a magneto-torque system (RIU)

    § Designed of an FPGA in charge of commanding an optical sensor

     

    Education

     

    10/2009 – 06/2010

    Master in Automation and Robotics. Stopped

     

    Technical University of Madrid (UPM, ETSII) – Madrid, Spain

     

    w Automation

    w Control

    w Robotics

    w Computer vision

     

    10/1999 – 06/2007

    MSc Telecommunications Engineering

     

    University of Las Palmas de Gran Canaria (ULPGC, ETSIT) – Canarias, Spain

     

    w Telematic

    w Electronic and Automation

    w Signals and Communications

    w Economics, Mathematics and Physics

     

    Personal Skills

     

    Mother tongue

    Spanish

     

    Other languages

    English, Dutch (basic)

     

    Communications skills

    w Clarity and concision

    w Confidence

     

    Organisational skills

    w Leadership, I have been responsible of small groups of people, couching and delegating tasks

    w Planning, as part of FPGA leader I must always define  project tasks and milestones

     


    Job-related skills

    w Quality, currently as group leader I have defined quality processes and methodology of design & verification

    w Analytical thinking and Problem solving skills, in my daily work I have always been analytical and I have been searching for the best&simplest solution

    w Work under pressure, I have started several time projects already delayed and/or with tight project planning

    w Fast learning, I have always been working in projects completely different in technical knowledge or field. I am also good in getting quickly involved in projects already started

     

    Computer skills

    w Microsoft Office tools

    w Microsoft Project

    w Matlab & Simulink

    w VHDL, VERILOG, SystemC, PSL

    w Modelsim, HDS-Designer, ActiveHDL, Synplify, Libero, ISE, Cadence Spectre

    w C/C++, Bash, TCL, Perl, Java, ADA, Visual Basic

    w Doors

    w Linux

    w WaveForm, Labview

     

    FPGAs

    w Microsemi: RTSX, RTAX, ProASIC3

    w Xilinx: Spartan3, Spartan6, Virtex7

     

    Standards

    ECSS-Q-ST-60-02C, SpaceWire, RMAP, SpaceFibre, CANOpen

     

    Other skills

    I am able to work either in a team or alone

     

    Additional Information

    Projects

    Master Thesis: Development of a network interface for Network-on-Chip architecture (NoC) with QoS assurance. Awarded with honours distinction

     

    Courses

    Introduction to Artificial Intelligence Course (2011). Online Stanford University

     

    Others

    Flying Satellites with my own designs in SPOT6, KazEOSat-1, Sentinel-2A


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