French, 53 years old
Image Sensors Development Expert with significant manufacturing experience.
Since July 2015 SOFRADIR: VP New Product Introduction: Member of the board of Directors. SOFRADIR is the world leader (outside US) in infrared detectors. Leading a team of project managers responsible for the development of new products using MCT, InGaAs, InSb and QWIP technologies.
2013-> June 2015 SOFRADIR: Deputy of CTO. Leading a team of 35 people in charge of designing new technology blocks for future products. Heading the activity of silicon circuits design, electronics and software development for the whole video chain. On top of this activity Deputy CTO for Program management. R&D staff is around 200 people.
2011 -> 2013 SOITEC: Program Manager for Smart Cell Incubator for CPV market.. Responsible for project execution from development with academics partners to industrialization. Responsible of a R&D budget of ~ 15M$/year. Accountability for program execution. Leading a team of 11 people in 3 different countries.
2005 -> 2011 STM: R&D Director: Technology Line Manager for CMOS Image Sensors. Responsible for program definition and execution for a major division of ST (CIS: 550M$) Responsible of a R&D budget of ~ 40M$/year. Definition of technical priorities. Accountability for budget and program execution.
2004 -> 2005 STM: Industrial Process Integration responsible in Crolles2 Alliance (300mm facility) Responsible for 0.13μm and 90nm process integration. Co-leader of a group of 19 people from ST, Philips, Freescale.
2001 -> 2003 STM: Embedded Memories Process Development Manager Responsible for 120, 90, 65nm eDRAM and innovative RAM solutions Process development. Leading a group of 11 people from ST, Philips, Motorola, LETI and TSMC
1999 -> 2001 STM: New Embedded Application Manager Crolles1 France (200mm facility) Responsible for embedded Image Sensors, eDRAM and NVM Process development in 0.15, 0.18, 0.25μm technologies.
1998 STM: Responsible for embedded OTP (One Time Programmable) memory development. Agrate Italy
1996 -> 1997 STM: Device engineer. Crolles. Process integration industrial team 0.35μm CMOS
1995 -> 1996 STM: Process development 0.35μm CMOS Design rules definitions, Design support R&D team.
1989 -> 1995 STM: SPICE device modelling responsible for CMOS processes of Crolles plant: CMOS Modelling 0.5um and 0.35um. Grenoble plant: Bipolar Modelling for process BiCMOS 1.2μm and 0.7μm.
English Fluent Italian Fluent German Written
1988 : Ph D Thesis. Doctorat de l'Université Scientifique et Médicale de Grenoble. Physics Microelectronics option. Subject: Contribution to the electrical modelling of transistor Silicon On Insulators. Application to transistors Silicon on Sapphire.
Management Project management in multicultural environment. Budget and resources allocation control. Physics Semiconductor device physics. Photovoltaic CPV market, Cost of energy, Module and system optimization. Electronics Design and processing of ICs, modelling of electrical behaviour, tests and measurements of devices, analog and digital design.
Culture Amateur astronomy + imaging, Amateur photography. Sport Mountain bike, jogging, country skiing, motorbike.
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