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Wed, 22 Nov 2017 19:00:00 +0100
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Wed, 22 Nov 2017 15:09:00 +0100
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Mon, 20 Nov 2017 17:00:00 +0100
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Mon, 20 Nov 2017 16:30:00 +0100
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Mon, 20 Nov 2017 00:00:00 +0100
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Sat, 18 Nov 2017 13:03:00 +0100
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Sat, 18 Nov 2017 08:00:00 +0100
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Fri, 17 Nov 2017 00:00:00 +0100
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Thu, 16 Nov 2017 15:07:00 +0100
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Thu, 16 Nov 2017 14:04:00 +0100
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Wed, 15 Nov 2017 19:33:00 +0100
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Wed, 15 Nov 2017 12:00:00 +0100
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     Date Submitted:01-05-2017
     Last Modified:01-05-2017 (04:37)
    Job information
     Current job:Radiation Effects Engineer
     Employment Term:Permanent
     Job location:Anywhere
     Date available:immediately
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators, , , Launch Systems

    I am a Brazilian-Italian with experience in computer engineering and emphasis on programmable systems. As an undergraduate student, I worked in the project of the first Brazilian nanosatellite, the NanoSatC-BR1. My main task was the project of the embedded software of the satellite’s onboard computer. My bachelor degree thesis focused on the analysis of single event effects on fault-tolerant memory architectures at circuit level by using a SPICE simulator. My master degree was focused on the characterization of programmable mixed-signal system-on-chip devices and evaluation of fault-tolerant techniques under radiation. The main case-study device was the Microsemi SmartFusion. My Ph.D. focused on analyzing the reliability and performance trade-offs on programmable system-on-chip devices under radiation. The main case-study device was the Xilinx Zynq-7000. Some side projects include: project and development of one of the payloads of the second Brazilian nanosatellite, the NanoSatC-BR2; project and development of hardware accelerators for Xilinx devices using the Vivado High-Level Synthesis tool; project and development of hardware with communication interfaces, such as UART, I2C, SPI, Gigabit Ethernet, SERDES, etc.; development of a fault-tolerant manager core to perform dynamic partial reconfiguration in Xilinx devices; development of a fault injection platform for Xilinx devices; project, development, and evaluation of fault-tolerant techniques for FPGAs, System-on-Chips, and Microprocessors; realization of radiation experiments in the several research institutes where I have collaboration works, such as the Universidade de São Paulo (USP), European Organization for Nuclear Research (CERN), National Research Nuclear University (MEPhI), Los Alamos National Laboratory (LANL), and Rutherford Appleton Laboratory (RAL-ISIS). Furthermore, I am a quick and self-learner and I can handle well working under pressure and with short deadlines.




    2013 – 2017                Ph.D. in Microelectronics

    Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil.

    Degree thesis: Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices.

    Research funding: CAPES, Brazilian Research Agency.


    2011 – 2013                Master’s degree in Electrical Engineering

    Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil.

    Degree thesis: Characterization of Programmable Logic Devices and Systems-on-Chips for Total Ionizing Dose and Single Event Effects.

    Research funding: CNPq, Brazilian Research Agency.


    2007 – 2010                Bachelor’s degree in Computer Science

    Universidade Federal de Santa Maria (UFSM), Santa Maria, Brazil.

    Degree thesis: Analysis of Single Event Effects in the Architectures of Memory Cells DICE and Norley.

    Research funding: CNPq, Brazilian Research Agency.





    2015 – 2016                Cooperation Associate at European Organization for Nuclear Research (CERN), Geneva, Switzerland

    Activity: Research of radiation hardness assurance methods for All Programmable Systems-on-Chips (APSoCs). The research involves the radiation testing of state-of-the-art devices, targeting devices embedding a FLASH/SRAM-based FPGA and at least one ARM Cortex processor.


    2013 – 2014                Guest Researcher at Politecnico di Torino, Torino, Italy

                                      Activity: Development of a fault-tolerant manager core for dynamic partial reconfiguration in Xilinx FPGAs.


    2007 – 2010                Intern at Instituto Nacional de Pesquisas Espaciais (INPE), Santa Maria, Brazil

    Activity: Project of the embedded software of the NanoSatC-BR1, the first Brazilian nanosatellite.





    Mother tongue            Portuguese

    Other language           English

    Understanding: Fluent   |   Speaking: Fluent   |   Writing: Fluent


    Social skills                Excellent group interaction skills due to the constant participation in research and development projects. Good tasks organization skills acquired by working with multiple projects with short deadlines, such as preparing and performing radiation tests in electronic components in the research institutions where I have collaboration works. Perseverance concerning the persecution of personal and professional objectives.


    Computer skills           Operating systems: Microsoft Windows, Linux.

    Hardware: FPGAs, Microprocessors/Microcontrollers, Heterogeneous Hardware, VHDL, and High Level Synthesis (HLS).

    Programming: C, C++, Assembly, Python, TCL, Shell scripting, and Java.

    Tools and IDEs: Xilinx Design Tools (ISE, Vivado, and Vivado HLS), Microsemi Libero Toolset, ModelSIM, Keil Tools for ARM, Eclipse, and SPICE-based simulators.

    Good at debugging hardware and software problems.





    Analyzing Reliability and Performance Trade-offs of HLS-based Designs in SRAM-based FPGAs under Soft Errors. L. A. Tambara, J. Tonfat, A. Santos, F. L. Kastensmidt, N. H. Medina, N. Added, V. A. P. Aguiar, F. Aguirre, and M. A. G. Silveira. IEEE Transactions on Nuclear Science, 2017. DOI: 10.1109/TNS.2017.2648978.

    Register File Criticality and Compiler Optimization Effects on Embedded Microprocessor Reliability. F. M. Lins, L. A. Tambara, F. L. Kastensmidt, and P. Rech. IEEE Transactions on Nuclear Science, 2017. (approved for publication)

    Radiation-induced Failure Impact in All Programmable SoCs. L. A. Tambara, P. Rech, E. Chielle, J. Tonfat, and F. L. Kastensmidt. IEEE Transactions on Nuclear Science, 2016. DOI: 10.1109/TNS.2016.2522508.

    S-SETA: Selective Software-Only Error-Detection Technique Using Assertions. E. Chielle, G. S. Rodrigues, F. L. Kastensmidt, S. Cuenca-Asensi, L. A. Tambara, P. Rech, and H. Quinn. IEEE Transactions on Nuclear Science, 2015. DOI: 10.1109/TNS.2015.2484842.

    Exploring Design Diversity Redundancy to Improve Resilience in Mixed-Signal Systems. C. P. Chenet, L. A. Tambara, G. M. de Borges, F. L. Kastensmidt, M. S. Lubaszewski, and T. R. Balen. Microelectronics Reliability, 2015. DOI: 10.1016/J.MICROREL.2015.08.011.

    Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA. F. L. Kastensmidt, L. A. Tambara, D. V. Bobrovsky, A. A. Pechenkin, and A. Y. Nikiforov. IEEE Transactions on Nuclear Science, 2014. DOI: 10.1109/TNS.2014.2369008.




    Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC. A. B. de Oliveira, L. A. Tambara, and F. L. Kastensmidt. Lecture Notes in Computer Science, 2017. DOI: 10.1007/978-3-319-56258-2_17.

    Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. A. F. dos Santos, L. A. Tambara, F. Benevenuti, J. Tonfat, and F. L. Kastensmidt. Lecture Notes in Computer Science, 2017. DOI: 10.1007/978-3-319-56258-2_18.

    Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs. L. A. Tambara, J. Tarrillo, F. L. Kastensmidt, and L. Sterpone. FPGAs and Parallel Architectures for Aerospace Applications. 1ed.: Springer International Publishing, 2016. DOI: 10.1007/978-3-319-14352-1_9.

    Neutron-induced Single Event Effect in Mixed-Signal Flash-based FPGA. L. A. Tambara, M. S. Lubaszewski, T. R. Balen, P. Rech, F. L. Kastensmidt, and C. Frost. FPGAs and Parallel Architectures for Aerospace Applications. 1ed.: Springer International Publishing, 2016. DOI: 10.1007/978-3-319-14352-1_14.

    Multiple Fault Injection Platform for SRAM-Based FPGA Based on Ground-Level Radiation Experiments. J. Tonfat, J. Tarrillo, L. A. Tambara, F. L. Kastensmidt, and R. Reis. FPGAs and Parallel Architectures for Aerospace Applications. 1ed.: Springer International Publishing, 2016. DOI: 10.1007/978-3-319-14352-1_10.

    Method to Analyze the Susceptibility of HLS Designs in SRAM-based FPGAs under Soft Errors. J. Tonfat, A. Flores, F. L. Kastensmidt, and L. A. Tambara. Lecture Notes in Computer Science, 2016. DOI: 10.1007/978-3-319-30481-6_11.

    Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects. L. A. Tambara, A. F. Almeida, P. Rech, F. L. Kastensmidt, G. Bruni, and C. Frost. Lecture Notes in Computer Science, 2015. DOI: 10.1007/978-3-319-16214-0_28.




    Evaluating the Use of APSoCs for CERN Applications. L. A. Tambara, E. Chielle, F. L. Kastensmidt, G. Tsiligiannis, S. Danzeca, M. Brugger, and A. Masi. European Conference on Radiation and its Effects on Components and Systems (RADECS), 2016.

    On the Characterization of Embedded Memories of Zynq-7000 All Programmable SoC under Heavy Ions and Protons Induced Single Event Upsets. L. A. Tambara, A. Akhmetov, D. V. Bobrovsky, and F. L. Kastensmidt. European Conference on Radiation and its Effects on Components and Systems (RADECS), 2015. DOI: 10.1109/RADECS.2015.7365643.

    Reliability on ARM Processors against Soft Errors by a Purely Software Approach. E. Chielle, F. Rosa, G. S. Rodrigues, L. A. Tambara, R. Reis, and S. Cuenca-Asensi. European Conference on Radiation and its Effects on Components and Systems (RADECS), 2015. DOI: 10.1109/RADECS.2015.7365660.

    Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC. L. A. Tambara, F. L. Kastensmidt, N. H. Medina, N. Added, V. A. P. Aguiar, and M. A. G. Silveira. IEEE Radiation Effects Data Workshop (REDW), 2015. DOI: 10.1109/REDW.2015.7336716.

    Soft Error Rate in SRAM-based FPGAs under Neutron-induced and TID Effects. L. A. Tambara, J. Tonfat, R. Reis, F. L. Kastensmidt, E. C. F. Pereira, R. G. Vaz, and O. L. Gonçalez. IEEE Latin American Test Workshop (LATW), 2014. DOI: 10.1109/LATW.2014.6841920.

    Decreasing FIT with Diverse Triple Modular Redundancy in SRAM-based FPGAs. L. A. Tambara, F. L. Kastensmidt, P. Rech, and C. Frost. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014. DOI: 10.1109/DFT.2014.6962070.

    Power Dissipation Effects on 28nm FPGA-based SoC Neutron Sensitivity. G. Bruni, P. Rech, L. A. Tambara, G. L. Nazar, F. L. Kastensmidt, R. Reis, and A. Paccagnella. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2014. DOI: 10.1109/VLSI-SoC.2014.7004195.

    Evaluating the Effectiveness of a Diversity TMR Scheme under Neutrons. L. A. Tambara, J. R. Azambuja, E. Chielle, F. Almeida, G. L. Nazar, P. Rech, M. S. Lubaszewski, F. L. Kastensmidt, and C. Frost. European Conference on Radiation and its Effects on Components and Systems (RADECS), 2013. DOI: 10.1109/RADECS.2013.6937382.

    TID in a Mixed-Signal System-on-Chip: Analog Components Analysis and Clock Frequency Influence in Propagation-Delay Degradation. L. A. Tambara, F. L. Kastensmidt, E. C. F. Junior, O. L. Gonçalez, T. R. Balen, P. C. C. de Aguirre, I. Arruego, and M. S. Lubaszewski. IEEE Radiation Effects Data Workshop (REDW), 2012. DOI: 10.1109/REDW.2012.6353710.

    Neutron-induced Single Event Effect in Mixed-Signal Flash-based FPGA. L. A. Tambara, F. L. Kastensmidt, M. S. Lubaszewski, T. R. Balen, P. Rech, and C. Frost. European Conference on Radiation and its Effects on Components and Systems (RADECS), 2012.


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