Highly motivated Design Engineer with deep knowledge of embedded systems, FPGA, C, Verilog HDL and VHDL. Undertaking a contract job as an Electronics Design & Firmware Engineer in GE.
Keen, pragmatic, conscientious, analytical, hardworking individual who is ambitious and goal orientated. Now seeking next rewarding career opportunity to demonstrate substantial abilities and make an effective contribution in a successful product focused team.
11/4 years’ experience as a system engineer
51/4 years’ experience as a design engineer (FPGA developer and embedded systems)
Excellent knowledge of Verilog, VHDL, C and C++languages
Experience of using ASIC (Synopsis and Cadence ASIC design tools), Lab View, MATLAB, Altium and Visual Studio – with a high level of dexterity with Code Compose Studio, Multisim, ModelSim and Xilinx design suit, Vivado design suit, Altera design suit.
Experience of using sub version system (GitHub, SVN)
Understanding of Cadence, PLC, System Verilog, and UVM methodology
Meet tight and demanding deadlines under pressure
Able to communicate proactively with clients and senior management
Punctual and enthusiastic person who works well individually and as part of a team
Willing to adapt into different working environments and use skills to contribute positively to any situation
May 2017 – To Date
Employer: GE Power
Job Title: Electronics Design & Firmware Engineer
Series 5 Valve Base Electronics
Series 6 Valve Base Electronics
Sub Module (Gate Electronics) Verification
Renovating and Testing series 5 VBE (valve base electronics) Altera base design to Xilinx environment.
Designing and developing series 6 VBE firmware architecture. and substantial hands-on contributions to product with direct ownership of various implementation, and ongoing support issues.
Implementation, development and Testing of various communication protocols like PON, PCIe, 1G Ethernet, UART Interfaces, I2C.
Used System Verilog to test and verify Gate Electronics Firmware.
Next Generation Series 6 VBE firmware architecture.
Aug 2016 – May 2017
Job Title: Electronics Engineer
Control of temperature of ‘new large tube rig’. (QuRapID)
Assessment of concepts and techniques for temperature control for QuRapID using PID controller in VHDL on Spartan 6.
Designing spectrometer electronics using Altium and developing algorithms in C (controlling CCD image sensors) using PIC 32 microcontroller and developing .Net testing platform to communicate with spectrometer electronics.
Testing of SPI, UART Interfaces.
Solenoid Timer base control.
Planned and developed algorithms for PID Controller for QuRapID.
Automated QuType for Lab Testing on real Virus.
Nov 2014 – Mar 2016
Job Title: System Engineer
Transmission, Tracking and Control (TT&C) Communication system for remote sensing satellite
AES Core Integration in TCP/IP communication on Spartan 6
Interfacing of Si8900/1/2 with FPGA Using SPI protocol
Assessment of concepts and techniques for satellite TT&C communication systems for both space and ground segment
Designing and developing algorithms in C for on board satellite data handling computer to ground segment
Development, integration and testing of satellite central terminal unit (CTU) using ECSS standards by using SysBIOS
Testing of CANBUS, SPI, UART, Serial and parallel NAND Flashes.
Designed architecture and developed algorithms for on board satellite data handling computer to ground segment communication
Tested interfaces like CANBUS, SPI with Taxes Instrument microcontroller
Interfaced SPI protocol for commination with ADC.
Mar 2014 – Nov 2014
Job Title: Embedded System Developer
Modification of Cattron Control Joystick style transmitter
Developed device drivers for various hardware peripherals such as serial-EEPROM and RTC on I2C and SPI
Coding to support Cattron on-board analogy input channels, schedule blocks and auto-detection of hardware resources configured by the user
Design, implementation and debugging firmware in C using Microchip and logic analyser
Implemented test case for MMCU module of Crane on National Instrument Test Stand tool
MMCU test unit of crane and train transmitter
Aug 2012 – Aug 2013
Employer: Open Silicon
Job Title: Design Engineer
Micron NAND Flash Model and Controller IP Core
Design and Implement NAND flash model using Micron standard (in System Verilog and C) for timing requirement and FSM respectively
Provide NAND Flash Controller Testing Environment by using ONFI standard
Using Synopsys and Xilinx tools for development in Verilog, System Verilog and C
Testing storage protocols using UVM Environment
Planning, organising, and executing design projects resulting in enhancement of existing products
Completed NAND Flash Model and Controller tested in system Verilog.
Sep 2011 – Jul 2012
Employer: Technological Research Solution (Teresol)
Job Title: FPGA Design Engineer
H.264 Video Compression IP Core
Testing of DVM (Digital Video Manager)
Performed detailed calculations to broaden DVM product standards and specifications
Implement RS 232, 485 interfacing techniques
Implementation of H.264 video compression technique in an IP camera
Worked on DDR2 RAM interfacing in FPGA Spartan 3 and Spartan 6
Development, testing and documentation of RTL level modules
Developed residual generator in H.264 video compression IP core.
Tested DVM in Xilinx and Spartan 6.
2007 – 2011 BEng Electronics
CGPA 3.41/4.00 National University of Science and Technology
2005 – 2007 Maths, Physics, Chemistry
A, A, A The Educators College
Interest in cultural anthropology
Energetic player of Table tennis
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