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    Personal information
    Contact information
    Candidate Profile
     Date Submitted:23-08-2019
     Last Modified:28-08-2019 (10:44)
    Job information
     Current job:Radiation Effects Engineer
     Employment Term:Permanent
     Job location:Anywhere
     Date available:immediately
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators, ,
     KeywordsFault-tolerance, CubeSats, SRAM FPGAs, Reliability Modelling, SEUs, SEEs, Fault-injections, Reconfiguration, Research, Embedded Systems, Reconfigurable Architectures, Dynamic Partial Reconfiguration

    Areas of Specialization

         High Performance Computing / High-Level Synthesis (HLS)
            FPGA Digital Design / Electronic Design Automation 
            System-on-Chip Architectures / SW/HW co-design 
            Fault-tolerant FPGA-based Systems / Single Event Effects Testing     
            Embedded Software Engineering / Real-time Operating Systems 
            Reconfigurable Architectures / Dynamic Partial Reconfiguration (DPR)   


    Ph.D. (Aug. 2014 -- June 2019) 
    University of New South Wales -- Computer Science and Engineering, Sydney, Australia 
    Thesis: High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms. [Online]. Available:
    • I proposed novel fault-tolerant techniques and CAD tools that mitigate radiation effects in safety-critical and high reliability FPGA-based applications. In order to test the proposed techniques and CAD tools, I designed, implemented and tested hundreds of circuits on Virtex-6 and Artix-7 FPGAs as well as Zynq-7000 SoC FPGAs.
    • I had the opportunity to put into practice my expertise in fault-tolerant FPGA computing systems by developing the RUSH satellite payload ( for the UNSW QB50 project. The main purpose of the project was to test the effectiveness of fault-tolerant design techniques, such as Triple Modular Redundancy (TMR) with dynamic partial reconfiguration, on Artix-7 200T FPGAs. My main activity on the RUSH project was to develop the specifications of the payload, RTL design, as well as design verification and debugging. The RUSH payload has been sent to space twice. The first payload was deployed in Low Earth Orbit (LEO) on April 19th 2017 and re-entered the atmosphere on December 3rd 2018, while the second payload is currently operating in the International Space Station (ISS).
    • Dynamic Partial Reconfiguration (DPR) on the Zynq-7000 SoC (PCAP+ARM).
    • DPR on Artix-7 and Virtex-6 FPGAs (ICAP+Microblaze).
    • RTL design and verification with Verilog, SystemVerilog and VHDL.
    • High Level Synthesis with LegUp and TLegUp.
    • Design automation with Vivado TCL and Python.
    • Circuit debugging with ChipScope. 
    • Bitstream and essential bits analysis with Java
    • Fault-injection tools to emulate configuration memory upsets with DPR in Artix-7  and Virtex-6 FPGAs as well as Zynq-7000 SoCs.
    • Reliability, availability and energy consumption models. 

    M.Sc. (Oct. 2010 -- Oct. 2013)
    University of Piraeus -- Department of Informatics, Athens, Greece 
    Thesis: Development of a soft-error vulnerability analysis framework for FPGA devices.
    • Developed a framework to analyse the soft error vulnerability of Virtex-5 and Virtex-6 FPGA circuits.
    • Developed a simulated annealing placer for Virtex-5 and Virtex-6 FPGA, which required a deep understanding of all architectural details of Xilinx FPGAs.
    • EDIF, XDL, RapidSmith.
    • Dynamic partial reconfiguration. 
    • Analysis of Xilinx bistreams and essential bits files.

    B.Sc. (Sep. 2002 -- Apr. 2008)
    Technological Educational Institute of Athens -- Department of Electronics, Athens, Greece 
    Thesis: Development of an embedded transmittance and fluorescence meter.

    Research Engineer Intern (Dec. 2018 -- July 2019)
    Xilinx Asia Pacific. Ltd. -- Xilinx Research Labs, Singapore   
    • Accelerated computational intensive functions of the Hyperledger Fabric blockchain framework with PCIe FPGA boards (Kintex Ultrascale FPGAs). The acceleration platform was developed with Xilinx SDAccel and Golang. 
    • High-performance computing, SW/HW partitioning, HLS, SDAcell.
    • Blockchain, cryptography,  socket programming. 

    Research Engineer (Mar. 2014 -- Jul. 2014)
    University of Piraeus -- Embedded Systems Lab  (, Athens, Greece
    • Worked on the so-called ``Validation of Time and Space Partitioning (TSP) architectures in emerging space-craft/satellite on-board applications'' project. In this work, I ported the XtratuM hypervisor ( on a LEON3 soft-processor, which was implemented on a Xilinx Virtex-5 FPGA. Two bare-metal C applications, a FreeRTOS application and a Linux-based application were developed and hosted on the XtratuM hypervisor.    
    • Real-time operating systems, FreeRTOS.
    • Safety-critical and security-critical aerospace applications. 
    • Bare-metal hypervisors, XtratuM hypervisor.
    • Multiple Independent Levels of Security/Safety (MILS) architectures.

    Electronics Engineer (May 2010 -- Feb. 2014)
    National Observatory of Athens -- Geodynamics Institute (, Athens, Greece
    • Developed embedded systems to remotely control and monitor unattended scientific equipment (e.g., seismometers, magnetometers) and network devices (e.g., satellite modems) on communication failures. This project increased the availability of these remote stations and also reduced the cost of their maintenance.
    • Developed embedded systems and Linux-based services for the following national projects: 
            • Hellenic geomagnetic array (
            • Hellenic national tsunami warning center (
            • Hellenic national seismic network (
            • Acropolis restoration service.  (
    • All-around working experience, such as development of low-power embedded systems, PCBs, data acquisition systems, Linux-based services.

    Electronics Engineer (Sep. 2009 -- Apr. 2010)
    Adicon Industrial Automation, Athens, Greece
    • Industrial automation system architect consultant.

    Mandatory National Service (Aug. 2008 -- Aug. 2009)
    Hellenic Army, Greece

    Electronics Engineer Intern (May. 2007 -- Oct. 2007)
    Elecromagnetic Variations Research Laboratory, Athens, Greece
    • RS-232 to Ethernet converter.
    • Low-cost transmittance and fluorescence meter.
    • PCB design, circuit simulation.
    • Embedded systems design, digital signal processing, Fast Fourier Transform (FFT Radix-2) on AVR-8bit MCU.

    Teaching Experience

    Tutor (Q2, 2014 -- 2017)
    University of New South Wales, Sydney, Australia
    • Digital circuits and systems (COMP3222).
    • VHDL, Intel FPGAs, Digital circuit design.

    Tutor (Q1, Q2, 2009 -- 2010)     
    Technological Educational Institute of Athens, Athens, Greece
    • Microprocessors.
    • Microcontrollers and embedded systems.
    • x86 & AVR 8-bit MCU architectures. 
    • Assembly, embedded C. 
    • Communication protocols, e.g., RS-232, RS-485, I2C, SPI.

    Postgraduate Research Support Scheme (PRSS) for Conference Travelling. (2016)
    Australian Postgraduate Award (APA) Scholarship for Study Towards a Ph.D. (2014)

    • I value honest and loyal people and I try to be one of them. 
    • I am always motivated to grow and learn. Staying still is my worst enemy. 
    • Having worked in various companies and organisations, as well as, having lived in three different countries (Greece, Australia and Singapore) has transformed me into a highly flexible and adaptable person.   
    • I love nature, rock climbing, diving and piloting small planes.

    Papers in Refereed Journals:
    [1] D. Agiakatsikas, E. Cetin, O. Diessel, "FMER: an energy efficient error recovery methodology for SRAM-based FPGA designs'', IEEE Transactions on Aerospace and Electronic Systems (TAES), 2018, vol. 54, no. 6, pp. 2695--2712. [Online]. Available:
    [2] Z. Zhao, N. T. H. Nguyen, D. Agiakatsikas, G. Lee, E. Cetin and O. Diessel, "Fine-grained module-based error recovery in FPGA-based TMR Systems'', ACM Reconfigurable Technology and Systems (TRETS), vol. 11, no. 1, March 2018, pp. 4:1--4:23. [Online]. Available:
    [3] N. T. H. Nguyen, D. Agiakatsikas, Z. Zhao, T.Wu, E. Cetin, O. Diessel, and L. Gong, "Reconfiguration control networks for FPGA-based TMR systems with modular error recovery,''  in Microprocessors and Microsystems, 2018,  pp. 86--95. [Online]. Available:

    Papers in Refereed Conference Proceedings:
    [1] D. Agiakatsikas, G. Lee, T. Mitchell, E. Cetin and O. Diessel, "From C to fault-tolerant FPGA-based systems'', in IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Boulder, CA, 2018, pp. 1--1 [Online]. Available:
    [2] G. Lee, D. Agiakatsikas, T. Wu, E. Cetin and O. Diessel, "TLegUp: A TMR code generation tool for SRAM-Based FPGA applications using HLS'', in IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 129--132. [Online]. Available:
    [3] L. Gong, A. Kroh, D. Agiakatsikas, N. T. H. Nguyen, E. Cetin and O. Diessel, "Reliable SEU monitoring and recovery using a programmable configuration controller'', International Conference on Field Programmable Logic and Applications (FPL), Ghent, 2017, pp. 1-6. [Online]. Available: 
    [4] D. Agiakatsikas, E. Cetin, and O. Diessel, "FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs'', in International Conference on Field Programmable Logic and Applications (FPL), Lausanne, 2016, pp. 1-4. [Online]. Available:
    [5] D. Agiakatsikas, N. T. H. Nguyen, Z. Zhao, T.Wu, E. Cetin, O. Diessel, and L. Gong, "Reconfiguration control networks for TMR systems with module-based recovery,''  in IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington DC, 2016,  pp. 88--91. [Online]. Available:
    [6] G. Z. Zhao, D. Agiakatsikas, N. T. H. Nguyen, E. Cetin and O. Diessel, "Fine-grained module-based error recovery in FPGA-based TMR systems'', International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 101-108. [Online]. Available:    
    [7] N. T. H. Nguyen, D. Agiakatsikas, E. Cetin and O. Diessel, "Dynamic scheduling of voter checks in FPGA-based TMR systems'', International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 169-172. [Online]. Available:
    [8] L. Gong, T. Wu, N.T.H. Nguyen, D. Agiakatsikas, Z. Zhao, E. Cetin and O. Diessel, "A programmable configuration controller for fault-tolerant applications'',  International Conference on Field-Programmable Technology (FPT), Xi'an, 2016, pp. 117-124. [Online]. Available:
    [9] A. Sari, D. Agiakatsikas and M. Psarakis, "A Soft Error Vulnerability Analysis Framework for Xilinx FPGAs'',  ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA), Monterey, CA, 2016, pp. 237-240. [Online]. Available:
    Leadership and Services
    Reviewer Services for Journals:
    • ACM Reconfigurable Technology and Systems (TRETS) 
    • Microprocessors and Microsystems

    Reviewer Services for Conference Proceedings}]:
    • IEEE International Symp. on Field Programmable Custom Computing Machines (FCCM)
    • International Conference on Field-Programmable Technology (FPT)
    • International Conference on Field Programmable Logic and Applications (FPL)
    • IEEE International New Circuits and Systems Conference (NEWCAS)

    Co-supervision Service for B.Sc. and M.Sc. Students:
     • University of New South Wales -- Computer Science and Engineering   

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