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The launch of a NASA astronomy smallsat mission next year will be postponed by several months after the pandemic delayed assembly of key elements of the spacecraft. SpaceNews
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Wed, 05 Aug 2020 15:00:14 +0000
Commercial satellite operatorSES has selected SpaceX and United Launch Alliance to each launch two geostationary satellites designed to replace C-band capacity in the United States that the Federal Communications Commission is repurposing for 5G cellular networks.  SpaceNews
Wed, 05 Aug 2020 14:21:35 +0000
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The NASA astronauts who flew on the SpaceX Demo-2 commercial crew vehicle said they were pleasantly surprised at how well the Crew Dragon spacecraft performed. SpaceNews
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After months of delays and testing setbacks, a prototype of SpaceX’s Starship next-generation reusable launch vehicle made a brief “hop” flight Aug. 4 at the company’s South Texas test site. SpaceNews
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China is advancing the development of the Chang'e-7 lunar south pole mission and a complex campaign to study comets and return samples from a near-Earth asteroid with a single orbiter. SpaceNews
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19854 cvs - 598 jobs


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    Personal information
    Contact information
    Candidate Profile
     Date Submitted:01-10-2019
     Last Modified:01-10-2019 (08:22)
    Job information
     Current job:Electrical Engineer
     Employment Term:Either
     Job location:Anywhere
     Date available:within a month
     Industry:Civil Agencies/International Organizations, Satellite Manufacturers and Subcontractors, Satellite Operators, , , Launch Systems

    Clearance: Secret (Expired)





    Career Objective

    Seeking career as Electronics Engineer in areas of FPGA design, PCB Design, or C programming.




    Johns Hopkins University, Columbia, MD     Anticipated Graduation Date: December 2022

    Master of Science in Computer and Electrical Engineering                                                    


    The University of Texas-Pan American, Edinburg, TX   Graduation Date: December 2011

    Bachelor of Science in Electrical Engineering                 


    Work Experience


    Emergent Engineering, Austin, TX      February 2018 – Present

    Business Owner / Independent Contractor


    National Instruments, Austin, TX                                                                           

    Hardware Engineer – FPGA Designer

    Support large team by implementing an MMCM into their current Compact RIO design to provide capability to dynamically change clock rates of LVDS lines on a Kintex-7 Xilinx FPGA running on Labview FPGA platform utilizing Dynamic Reconfiguration Port over AXI4-Lite interface.


    L3 Technologies, Waco, TX                                                                                  

    Hardware Engineer – FPGA Designer

    Convert legacy code from Altera parts to Xilinx Spartan 6 part. Convert Altera schematics and megafunctions to VHDL to import into Xilinx design. Replace all Altera primitives with equivalent Xilinx primitives.

    Concurrent Design Engineering, Austin, TX                                                            

    Hardware Engineer – FPGA Designer/Schematic Capture

    FPGA Consulting on part recommendation, proper power supply design recommendation for Xilinx Kintex 7.

    Created Schematics for board design in Altium.

    Southwest Research Institute, San Antonio, TX                                                             

    Hardware Engineer – FPGA Designer

    FPGA Programming, programmed Xilinx KC705 Kintex 7 development board to utilize 1Gb Ethernet UDP packets for gathering telemetry data. RTL primarily written in VHDL some Verilog. Implemented DDR3 memory module to store data.

    Create technical documents for FPGA design and user guide.


    Firefly Aerospace, Cedar Park, TX        June 2017 – February 2018

    Avionics Design Engineer

    Performed System Architecture Analysis of vehicle Avionics systems.

    Designed hardware in the loop testing apparatus for avionics flight hardware.

    Programmed Spartan 7 FPGA Solenoid Drive Board: utilized 1 Gb Ethernet UDP packets

    Created design of Hardware In the Loop for Avionics testing purposes.


    Firefly Space Systems, Cedar Park, TX      November 2015 – December 2016

    Avionics Design Engineer – Power Systems

    Assisted in sourcing of 18650 Lithium Ion Cells.

    Assist with mechanical design of an 8 pack Lithium Ion battery coordinating with NASA Johnson Space Center.

    Designed Active Balancing Circuitry and Battery Management System for Lithium Ion battery pack using Altium PCB Board Design Software.

    Created Simulink test bench that allowed for test automation and collection of battery test data such as cell charge algorithms, discharge curves and cell characterization.

    Create requirements documents as needed.


    Northrop Grumman, Linthicum, MD      June 2011 – November 2015

    Hardware Engineer – FPGA Designer

    FPGA designer on multiple programs

    Responsible for overall design of several FPGA’s (Altera CPLD, Xilinx Virtex V, Xilinx Virtex VII).

    Create VHDL code for design (Interfaces learned: Common Bus, HDLC, I2C, SPI, Ethernet, RS-232, High Speed SERDES: 3 Gb and 10 Gb, JESD204B Receiver with line rate of 6.4 Gps, PCIe Gen 2).

    Created testbench for design and modeling in QuestaSim.

    Created test procedure for subsystem using Simulink UI with ML501 Xilinx Virtex V and VC707 Virtex 7 development boards.

    Implemented Microblaze processor in FPGA design for debugging purposes.

    Created partial reconfiguration tests on Xilinx Virtex 7 690T FPGA.


    BAE Systems, Nashua, NH             May 2011 – August 2011

    Wireless Communications Engineer Intern – WiFi Tester

    Working under the supervision of a more experienced engineer, was responsible for setting up a test bed for Denial of service of 802.11 networks. Tasks included:

    Researching for compatible software/hardware for testing requirements.

    Create Matlab GUI for test automation.

    Perform testing of DOS techniques for 802.11 networks.

    Document and report final results to compare results from previous testing.

    Accomplishments include gaining familiarity with setting up a proper test bed and learning about Azimuth channel emulator.


    Northrop Grumman, Linthicum, MD        May 2010 – December 2010

    Hardware Engineer Intern – Digital Systems

    Working under the supervision of a more experienced engineer, was responsible for building and testing a simulator chassis to exercise interfaces to a space vehicle. Test set simulated MIL-STD-1553 and SpaceWire interfaces, and enabled early integration with the vehicle equipment. Tasks included:

    Creating assembly and test documentation, including detailed schematic, cable drawings, and interface panel

    Working with technician to assemble chassis.

    Performing testing of chassis, including writing test procedure plan (50 pages).

    Interface with engineers to troubleshoot problems that occurred.

    Writing complete user's guide (48 pages) for delivery to customer.

    Accomplishments included gaining familiarity with seeing a job through from beginning to end including every last detail of the construction of the unit and its cabling. Also developed experience with VxWorks, Tcl (Tool Command Language), Visio, MIL-STD-1533, and SpaceWire.

    Responsible for FPGA design of Xilinx – Virtex 5 for DSP to output LVDS signals into an LVDS buffer interface. Tasks included:

    Writing VHDL code to implement 18 bit wide LVDS output.

    Creating memory core for FPGA to read data.

    Verifing input/output waveforms of VHDL code in ModelSim.

    Testing output waveforms on Logic analyzer.

    Developed experience with VHDL programming using ModelSim, Xilinx ISE, and Xilinx Core Generator


    Northrop Grumman, Linthicum, MD            May 2009 – August 2009

    Software Engineer/Hardware Engineer Intern – Digital Systems

    Responsible for troubleshooting preprocessor boards. Troubleshooting included debugging techniques using Max Plus II, Quartus II, and Corelis. Tasks included:

    Debugging computer software errors in C++ using Visual Studio and Workbench.

    Debugging JTAG chain using traditional debugging techniques.

    Assisting experienced engineer in coming up with Boundary Scan Test to make for easier troubleshooting.

    Accomplishments included gaining familiarity with JTAG chain of Altera devices. Developed experience using Quartus II, Max Plus II, and Corelis.



    Software consultant for IEEE organization. Responsible for creating workshops to provide entering engineering students exposure to the basic knowledge of software used by any engineer such as Matlab

    Institute of Electrical and Electronic Engineers, member Fall 2007 – Fall 2011


    Society of Mexican American Engineers and Scientists   Fall 2008 – Fall 2011


    Related Coursework

    RF/Microwaves, Programming in Unix/Linux, Electromagnetics, Signals and Systems, Microprocessor Systems,    Electronics I/II, Digital Systems I/II, Electrical Circuits I/II, Computer Science I/II (C++), Automatic Control, Communication Theory, Solid State Electronic Devices


    Technical Skills

    Programming Languages : VHDL, Matlab, C, Verilog, SystemVerilog, Java

    Operating Systems : Windows 98/NT/2000/XP, Unix (Solaris/Mac OS X), Linux (Ubuntu/Debian), Android

    Software / Tools : Matlab, Simulink, Lab View, Pspice, PuTTY, Hyperterminal, Corelis, Max Plus II, Quartus II, ModelSim, Questasim, Xilinx Vivado, Xilinx ISE, Corelis, Valor Enterprise 3000, Android SDK, Eclipse IDE, Microsoft Office (Word, Excel, Access, Power Point, Visio, Internet Explorer, IO Designer, DxDesigner, Altium, Notepad ++, UltraEdit, Beyond Compare, GIT, Tortoise SVN)

    Hardware and Equipment: ML501 Virtex-5 Evaluation Board, VC707 Virtex 7 Evaluation Board, VC709 Evaluation board, Arduino Illuminato,  Android IOIO Micrcontroller, Tektronix TLA 714 Logic Analyzer, Agilent technologies MS07104A Mixed Signal Oscilloscope, HP 891A Peak Power Analyzer, Agilent Digital Multimeter, Azimuth channel emulator


    Projects :

    Senior Design: Project leader of a radio system design which will take incoming text messages from a cell phone and read them aloud over the automobiles stereo system. Tasks included using agile project management to make goals for project, build application to be installed on cell phone and integrate all necessary hardware components.

    Christmas Light Design : Designing a Christmas light display which will play along to the beats of music. Tasks including programming arduino in C language for light timing and channel control, build solid state relays from scratch to use for TTL logic control of 120V AC channel.

    Vending Machine: Provide design for a vending machine which will contain time sensitive products. As a user interface used a mini6410 embedded system with Android OS and an Android application to act as a POS for customers.

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