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Ø Master Degree (1995-2001):
Ø At the:
Politecnico of Turin, final mark : 110/110 cum Laude
Ø Master Thesis: “Modal Tecniques for the electromagnetic analysis of passive components in ridge waveguides” Rel: Prof. Renato Orta, Prof. Riccardo Tascone, “Politecnico of Turin”.
Ø High school:
o Scientific License (1990-1995), final mark 60/60.
Ø English study
o British school, attended for nine years
o PET certification with merit
Good in reading, writing and conversation;
Preliminary English Test, University of Cambridge.
Ø French: scholastic level
Ø Strong knowledge of Radar Systems and communication systems (GSM UMTS)
Ø Knowledge of System Simulation/Signal Processing techniques and Matlab Language (> 5y)
Ø Capability to develop under Simulink environment simulation models for complex systems and functions;
Ø Architecture definition of electronic systems and Hardware/software partitioning;
Ø Strong knowledge of VHDL language and of Xilinx System Generator Tool for the design of logic circuits and communication interface (PCI, VME, RocketIO, HotLink) (>7 y);
Ø Knowledge of all the design flow for producing programming files for the FPGA starting from RTL-HDL description
Ø Knowledge of C language and of the VxWorks environment for the implementation of SW functions for embedded systems
Ø Model of proportional navigation based systems;
Ø Currently leading the activities of a group made by myself and four other engineers
July 2012-Today: Aresys SRL, MILANO
Qualification:Head of Electronic Developments Area
Market of operation: Remote Sensing
Ø Work Experiences at Aresys:
o Leading the development of a Real Time SarRadar Emulator tailored for an UAV paltform. The system is COTS based (Curtiss-Writght and 4DSP) and its purpose is to generate (@IF level) the echos as would been received by a SAR Radar Processor (targeted for UAV SAR) in order to test it in laboratory. The system has been developed for an important non European global player of defense industry.
o Built-up of Electronic HW/System Department. During first year of activities the area grew-up fastly and now reached an number of five engineers. Main project involving the area is the development of a low cost and reduced dimensions Radar Sensor and UAV SAR emulator.
o Leading the development of an FMCW Radar Sensor. Main sub-activities were (all internal developments):
§ System Architecture and Design;
§ System Simulations (Matlab/Simulink);
§ Software and FPGA/FW developments (VHDL, System Generator, C Language);
§ Local Oscillator / synthesizer developments;
§ Power Supply Unit;
§ Antenna and Transceiver are COTS modules;
o Development of a Simulink model for the simulation of the complete physical Layer of GSM communication system
April 2005-June 2012: Elettronica SPA, ROMA
Qualification:System Architect / Analyst and Digital Designer
Market of operation: Systems for Radar Electronic Warfare
Ø Work Experiences at Elettronica:
o Leading an italian founded project for the study and developement of Jamming Codes (special modulations for the deceive of infrared missiles). An important aspect of this project is the development of an engagement simulator (missile-target) to verify effectiveness of codes.
o Design at system level and leading developement of the SW for management and allocation of HW resources for a Laser DIRCM system (Direct Infrared Counter Measures)
o Design of a simulator of Missile Warning System made of:
§ HW COTS: Matrox Card for the acquisition and the processing of images, Power PC & VxWorks Curtiss-Wright, Host PC, HW for MIL-BUS-1553 management
§ SW for the management of communication, and of MMI interface. SW has been developed partially under Visual Studio partially under WindRiver-workbench environment.
§ Algo level SW for the Image Processing. Purpose was to analyze captured images in order to extract emitting sources
o Algorithmic study and implementation on FPGA, of a firmware aimed to phase goniometry. The developed block estimates azimuth and elevation of the Direction of Arrival of an emission using the measures of phase difference among different channels, provided from a digital receiver. Finally, the block converts the estimations from the local antenna-panel reference, into a fixed reference, knowing the navigation data.
o Development of a latest generation Digital Receiver Unit. One of the main challenges was to align four A/D converters of 3Gsps. The hardware used were the boards from VMETRO. In this project I actively worked either at the algo & specification phase or at HDL and SW development. (VHDL and C/VxWorks were the tools I used)
o Algorithmic-Architectural study for a Digital Down Converter, highly reconfigurable, multichannel in band 0-100 MHz, and IF band between 5 KHz e 5 MHz. Implementation of the DDC in Xilinx System Generator and prototypation on FPGA Xilinx Virtex-4.
o Rapid Prototyping Methodology: I lead succesfully a pilot project which purpose was to set up and demonstrate the “hardware in the loop” design methodolgy, where the Matlab/Simulink simulator, System Software, System Hardware work toghether according to the following tasks:
§ Matlab Simulink Simulator: transmits stimuli;
§ System Sofware: Implements software algos and controls, communicates with the hardware by means of memory mapped registers;
§ System Hardware: it is the digital architecture of the system (equivalent System Generator /VHDL) ;
The case study was the digital receiver, the most complex board present in the company. It was emulated on three boards Alpha-Data interconnected using serial links. Original source code was written in VHDL, a system Generator part has been added to it and all has been co-simulated whether in ModelSim environment or in Hardware.
May 2002 – April 2005at STMicroelectronics
Qualification: Digital Architect.
System of communication UMTS.
Ø Interesting Experiences (all developements are in VHDL):
o Research (in a multisite team) of innovative solutions to the problem of high communication speed for Turbo Codes (from tens to hundreds of Mbps) in particular providing efficient IPs for solving the “interleaver bottleneck”. In the ambit of this activity I produced a paper that I cite later on.
o Study and plementation of the Synopsys Power Methodology, for making estimates on dissipated power from digital circuits, investigating the impact of clock-gating on power consumption.
o Partecipation to the developement of a modem for the HSDPA channel of UMTS. It was made by an Inner Modem (based on a MMSE Equalyzer in the frequency domain) and an Outer Modem based on the Turbo Decoder
o Architectural study and implementation in VHDL of an FFT – Radix-4 of very small dimensions and variable number of points. The core was at the basis of the MMSE Equalyzer;
o FPGA: synthesis of components descripted in VHDL for FPGA Xilinx
o Post Place and Routesimulations also in Verilog (useful for power estimations) integrating SDF file for delays;
o Board: Use of 4DSP, Curtis-Wright, VMETRO, Alpha-Data and Nallatech boards.
Operating Systems: Solaris, Windows user level;
VHDL, C, Matlab at very high level;
C++ at superficial level
Cadence ncsim, Mentor Modelsim,
Simplicity Synplify Pro,
JTAG tools for Desing For Testability
Conrtanct & Salary
Full-time 7^CCNL Metalmeccanico
Salary of 52.000 Euro
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