CV: Flight hardware Designer, FPGA Designer, Avionics IPT Lead,


Personal information
Contact information
Candidate Profile
 Date Submitted:23-02-2011
 Last Modified:08-05-2014 (09:08)
Job information
 Current job:Flight hardware Designer, FPGA Designer, Avionics IPT Lead,
 Employment Term:Either
 Job location:Anywhere
 Date available:immediately
 Industry:Consulting/Engineering Services
 Keywordsflight Hardware , design, digital, FPGA, VHDL, SpaceWire, LEON3FT, Avionics Lead, dxdesigner, modelsim,

CLEARANCE: not currently active





“Robotic Lunar Lander Field Trial Avionics”  11ATC-0289/2011-01-2574

SAE 2011 Aerotech Congress & Exposition, Toulouse, France,

October 18-21, 2011,


Abstract/Poster - “Flexible, Low Cost, LEON3FT Processor based Architectures for Spacecraft” 

Low Cost Planetary Missions Conference, Johns Hopkins Applied Physics Laboratory, June 2011 


Presenter– “Universal Reconfigurable Processing Platform for Space Applications”

MAPLD Conference, Goddard Space Flight Center, September 2009



“SpaceCube : A Reconfigurable Computing Hardware Platform for Space Applications”

MAPLD Conference, Annapolis MD., September 2008



NASA Silver Metal (team award) for “Mighty Eagle” Lunar Lander 2012

NASA Exceptional Achievement Award for GSFC SpaceCube          2007

NASA ONE (team award) ISS Electronics Logistics Carrier        2006                



Moon Express Inc 1/13 – Present

Title: Sr Electrical Engineer

*Space Flight Digital Design of Aeroflex UT700 LEON3 (SPARC V8) processor board (first to fly UT700)

*Architected, Designed and Developed Dual MicroSemi ProAsic3 RT3000 FPGAs within Memory map of UT700 processor for spacecraft command and control.  (VHDL, ALDEC)   

*Avionics system design


FIBERTEK INC – 10/11 – 12/12

TITLE: Sr.Space Hardware/FPGA/Systems Engineer – Consultant

*Space Flight PCB and FPGA/VHDL (MicroSemi ProAsic) Design: International Space Station Avionics Communications Board for Cloud Aerosol Transport System(CATS) instrument: 100 BaseT Ethernet(new technology), Fiber Optic (new technology), 1553.

*Space Flight PCB and Xilinx V5 FPGA/VHDL design for NASA HQ sponsored new technology development of Fiber Optic Transceivers.(Worked with Goddard Space Flight Center Photonics group)

*SBIR: co-author for new Fiber Optic Transceiver technology development / demonstration with AFRL

*Flight hardware system design, requirements and documentation


TITLE:Sr.Hardware Lead/Avionics IPT Lead/FPGA Designer - Leased Worker

*Hardware Design (TRL6): New technology, Low Power, Flight Processor board for Robotic Lunar Lander Development Program (RLLDP) (DxDesigner, Hyperlynx Signal Integrity Analysis, Static Timing designer)

*LEON3FT processor (Aeroflex UT699),SpaceWire,CAN,Low Power <3 Watts

*IRAD: Demonstration distributing processing for hazard avoidance landing algorithms (Simulink, MatLab to VHDL conversion, Xilinx IDE)

*SpaceWire IRAD: Implementation of Xilinx V5 FPGA SpaceWire core and pcb design of Aeroflex 5 port SpW router board (Xilinx ISE, Synplify Pro, Aldec, DxDesigner)

*System and Avionics design for helicopter field trials of spacecraft landing imaging and sensors.

*Avionics Lead for joint APL/NASA Marshal Space Flight Center (ILN) International Lunar Lander / (RLLDP) Robotics Lunar Lander Development Program Studies:

RLEP – Cryogenic Lander w/rover, LPRP – Common Lander for Lunar Rim or Crater Floor, RLLDP – Lunar Polar Volatiles Lander, xPRP – Decadal Study Lander, NEA - Asteroid Lander, Warm Gas Test Article

*Designed inexpensive field test avionics board for custom Altimeter interfaces and 1 PPS distribution. (COTs integration, Altera EPLD design, Quartus, Aldec)

*Responsible for ILN/RLLDP Avionics budget, manpower and schedule (IPT Lead)

Test Conductor for Radiation Belt Storm Probes: L3 script and displays


GORDONICUS LLC   12/08 – 3/09

TITLE:Partner / FPGA and Board Designer

*Partnership with Aeroflex Inc to build Rugged/Space Flight computer with reconfigurable processing assets. Board design (DxDesigner)

*LEON3FT processor with dual Xilinx V4(FX60),RTAX2000,200Mbps Spacewire, CAN, 1553, cPCI, 8GByte FLASH, 18MByte RAM,3U size

*FPGA design using Gaisler / Aeroflex FPGA IP cores (Aldec, Synplify Pro, Xilinx ISE/EDK, Libero IDE)

*GRMON tool set and Gaisler IP development flow (Cygwin)

*Static timing and data flow analysis / System design / architecture

*Documentation and diagrams.



TITLE:Principal Digital Engineer (Military) - Consultant

*Military Software Radio Application (reverse engineering and multiple hardware platforms)

*FPGA design (VHDL) for SIGNET waveform within Modem Hardware Abstraction Layer (MHAL) environment 

*FPGA Architecture, Dataflow and Timing Diagrams

*Implementation of MHAL environment and Reverse engineering of SIGNET waveform.( Advanced ALDEC advanced simulation tool set, Modelsim)

*Waveform component verification using Matlab simulation

*Mixed Verilog and VHDL design port from Xilinx Virtex 4, FX60 to Altera   Cyclone III (Xilinx ISE, Quartus, Synplify Pro)

*FPGA design modifications to support multiple DSP and Microprocessor Interfaces on different development platforms. 

PLANNING SYSTEMS INC ( QinetiQ North America)   1/08 – 4/08

TITLE:Sr. System Analyst (Military)- Consultant

*Analysis and detailed design recommendations to bring existing proof of concept systems to meet military requirements.

*(DSSS) Direct Sequence Spread Spectrum Radio

*Distributed Calibrated GPS retransmission within a non-linear space

*Trade studies on RF components and FPGA radio component IP

*System diagrams, Technical Specifications, Requirements, Schedule

*Introduced unique simulation solution for end to end RF system simulation

*FPGA selection and architecture for (DSSS) Direct Sequence Spread Spectrum Radio and GPS systems


GODDARD SPACE FLIGHT CENTER, NASA (Sub to SGT Inc.)   6/07 – 12/07

TITLE:FPGA Designer/Lead and Systems Engineer (Space) – Consultant

*SpaceCube  – 4 x4 inch Reconfigurable Super Computer for Space: dual Xilinx V4 FX60 and dual Eclipse FPGAs

*System Design for RMS SpaceCube application flown on Hubble repair Mission, STS-125

*Baseline Hardware Design, Requirements, Functional Specification and Logistical support

*Dual flight Eclipse FPGAs design with embedded microcontroller. (VHDL)

*Flight FPGA Architecture, Synthesis, Simulation, Place & Route and Burn.

*Design port from development FPGA (Xilinx) to Flight FPGA (Aeroflex)

*First mission for Aeroflex Eclipse FPGAs.  Responsible for compatible tool sets required for development (Xilinx ISE, EDK, Quartus, Aldec, Synplify Pro, Precision and Qlogic)

*First mission to fly Aeroflex Eclipse and Xilinx V4 FPGAs


SWALES AEROSPACE   12/06 – 6/07

TITLE:Control and Data Handling (C&DH) Avionics Box Lead  (Space) - Consultant

*Quick turnaround C&DH redesign for TACSAT-3

*Subcontractor Management: SOW, Technical documents, Schematics and Contracts

*Spacecraft System Diagram, Data flow and Timing

*C&DH Box level: Requirements, Module Interfaces, Instrument Interface definitions, Specifications, Test Plans, and Test Procedures

*Multiple EGSE FPGA designs on inexpensive development boards to simulate instrument interfaces needed to verify subcontractor FPGA flight designs (VHDL) (Quartus)

*Flexible Bus Space Applications / Architecture



TITLE: Sr. Hardware Engineer/Avionics IPT Lead (Space) - Consultant

*Avionics Architect and Avionics Box Lead for International Space Station (ISS) Express Logistics Carrier

*Hardware Design: ISS Communications Interface module for SpaceCube (DxDesigner, PADs )

*Fiber Optic interface: hybrid device developed with SpacePhotonics

*Unique 10BaseT Internet implementation for Space (10BaseT )

*Architecture of Xilinx V4 and Aeroflex 6325 FPGAs

*Box and module level Functional specifications

* Box and module level System, Control, and Timing diagrams

*A/D interfaces based on APL TRIO devices

*High speed asynchronous data recovery via global clock phase shifting


NORTHROP GRUMMAN  4/04 – 12/05

TITLE:Sr. Hardware Engineer/Avionics Box Lead (Military) - - Consultant

*Mentor for new graduates

*Digital Box Lead for START (Special Threat Awareness Receiver Transmitter) Proof of Concept

*Box and Module level: Data Flow, Timing, Functional Diagrams and Requirements

*Adaptation of an existing three module single receiver system, to process data from multiple receivers, by making minor hardware modifications, system modifications and multiple new FPGA implementations.

*Architected and implemented multiple Xilinx Virtex FPGAs. (Synplify Pro, Xilinx Foundation tool set)

*Asynchronous high speed pulse detection

*VHDL implementation of complex algorithms for Multi-path processing/binning

*RF component control, shared memory, FIFOs, discretes serial ports,VME

*VHDL test beds and simulation verification (ModelSim)



TITLE:Sr.Hardware Engineer (Military) - Consultant

*Camera Data Processing Avionics Unit: Converted NTSC camera data to digital stream and provided output resolution options used on different aircraft avionics monitors. (Combination of COTS and digital design)

*Motherboard design: cPCI, LVDS and high power interfaces (Orcad, PADs)

*FEMA (Failure Event Mode Analysis) for avionics system

*Avionics video processing, communications and power control in Altera FPGA(VHDL) (Synplify Pro, Quartus)

*Video mixing, synchronization, decoding, de-interlacing and progressive scaling of composite NTSC square pixel video Lattice FPGA (VHDL)

*Multiple board/systems:diagrams, documents and hardware testing/verification



TITLE:Digital Hardware Engineer/Board Lead (Commercial) - Consultant

*Ground Station Radio boards for ICO and Thuraya mobile telephone satellite communications. (Transmit and Receive modules)

*Board design with new technology: cPCI, Hot Swap, BGAs and surface mount components. (Orcad, PADs)

*Altera FPGAs (Verilog), CompactPCI interface (PLX PLC9030 bridge), CompactPCI High Availability Hot Swap capability (Synplify Pro, Modelsim, Quartus)

*FPGA Dynamic control of PLLs, Automatic Gain Control, A/Ds and DACs. (I2C and SPI interfaces)

*ICO and Thuraya Earth Station Gateway Controller/Transceiver Hardware Specifications, System Verification, Commissioning Procedure, Director of software development used for worldwide Gateway commissioning.

*Wideband TDMA, E1 and T1 line protocols and hardware


DENIZ CORPORATION    6/95 - 12/95





TEMPLE UNIVERSITY(Academic & Athletic Scholarships)

Bachelor of Science in Electrical Engineering 1987


OTHER:Women’s Olympic Judo Team Finalist 1980

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