CV: Pre-doctoral researcher


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Candidate Profile
 Date Submitted:28-06-2012
 Last Modified:29-06-2012 (08:47)
Job information
 Current job:Pre-doctoral researcher
 Employment Term:Temp/Contract
 Job location:Anywhere
 Date available:within a month
 Industry:Satellite Manufacturers and Subcontractors, , , Launch Systems
 KeywordsFPGA, PCB design, Artificial intelligence, VHDL
CV


Objectives

Hardware engineer, FPGA designer, Electrical Engineer. Open for related positions.

 

Profile

I received a Diploma of Engineer in Computers, Computing Complexes and Systems, Networks from Moscow Aviation Institute (State University of Aerospace Technologies), Moscow, Russia and Diploma in Theory and Practice of Translation (Languages: English, Russian) from Institute of Foreign Languages of Moscow Aviation Institute. Over the past few years I have acquired a lot of practical skillscontributing few National and European projects, mostly dedicated to hardware development for control systems in National Space Industry. The key strengths that I possess include, but are not limited to more than 2-years practical experience in implementation of control system applications and my striving for continued excellence. I am a good team player and I like to get at the root of problems. The projects that I have participated were of control system applications, smart systems, sensors and signal processing algorithms. I also participated in international evaluation campaigns. Besides, the experiences from studying and working in Russia, The US and The Netherlands have expanded my knowledge of different cultures and languages.

Education

2012 – Present Pre-doctoral researcher in Smart systems and hardware intelligent algorithms (INCAS3, The Netherlands)

2005 – 2011  Diploma of Engineer in Computers, Computing Complexes and Systems, Networks (Moscow Aviation Institute)

2007 – 2010  Diploma of Linguist-Translator in Theory and Practice of Translation (Moscow Aviation Institute)


 

Business Roles

  • Pre-doctoral Researcher
  • Electronics Engineer
  • Hardware Design Engineer

 

Knowledge survey

Programming Languages

Verilog;VHDL, SystemC; C; C++, Assembler.

Operating Systems

Windows XP Professional, 7 Professional; Linux.
 

Methods

Optimization algorithms, digital signal processing, neural network signal processing, SW/ HW co-design, mixed analog-digital design, data protocol design, register-level programming.

Knowledge survey

FPGAs; Verilog programming; Hardware neural networks; mixed signal designing; PCB schematic design; PCB lay-out; Block diagram designing; creation of specifications; control-testing algorithms designing; algorithms modeling; Technical and Fundamental Analyses of hardware design; Digital Signal Processing Design, Techniques, and Theory;.

 

Applications and Tools

Cadence design tools (Orcad Pspice, Librarian, Design Entry HDL, PCB editor);P-CAD; Autocad;Actel Libero IDE;ModelSim; QuestaSim; Xilinx ISE; Quartus II; Cadence RTL compiler; Multisim; MathCad;MATLAB; MS Office; Visio.

 

Language

                                        Speak           Write            Read

       Russian                      native             native             native

       English                       fluent             fluent             fluent

       Dutch                         poor(learning)poor(learning)poor(learning)

       German                      poor               poor               poor

 

 

Project Descriptions

Period                      :2-2012  -  Present

Title                          : Hardware neural networks.

Partners                   :INCAS3, The Netherlands, Assen

Role                          : Pre-doctoral researcher

Domain                     :Smart sensor systems

Objective                 :to study the possible applications of neural networks and adaptive algorithms for sensor systems and future possibility of realization on reconfigurable hardware such as FPGA  .

 

Description

This program aims at studying the kinds of algorithms based on neural networks which can require to be implemented in parallel for realizing full potential and computation power of parallel neural networks.  


Examples of research questions that fall within this category are: (1) Real-time signal processing, (2) Sound sensory system for abnormal data extraction based on hardware (FPGA) neural networks, (3) “Real-time neuromorphic hardware. Thalamo cortical architecture on FPGA for auditory purposes, (4) Neural network for blind source separation based on hardware, (5) Adaptive context-independent hardware sensor system based on neural networks.



Tasks and activities

My task was to develop an overview possible nowadays technologies and proposal of the best solutions concerning sensors and sensor systems and, finally, to simulate and implement one of the algorithms for FPGA.  This work contributes an approach for smart signal processing. The approach is novel, it exploits new types of FPGAs and artificial neural networks adopted for hardware.

 

Results

I created a complete overview for recent technologies which showed the possibility of optimal implementation neural network on FPGAs and wrote a proposal with the main applications which can be used in INCAS3.  I simulated and tested the Radial basis function neural network, including simulation in MATLAB and then in Modalism, the module is prepared to be implemented for any types of FPGAs.

 

 

Applied methods, techniques, tools and hardware

 

Programming Languages    :   M-code;Verilog.

Operating Systems              :   Windows 7.

Methods                               :   Register level programming, testbenches.

Applications and Tools        :   Matlab, ModelSim.

 

 

 

 

Period                      :4-2011  -  1-2012

Title                          : Luna-Glob mission

Partners                   :Scientific technical innovation center “TECHCOM”, Moscow, Russia

Role                          : Electronics Engineer

Domain                     :On-board digital computing machine

Objective                 :Designing FPGAs and PCB layout for on-board digital computing machine

 

Description:

The goal of the project was to create on-board digital computing machine for Luna-Glob mission. Luna-Glob mission is a project of researching the moon by launching a satellite there and landing there alunar rover.  The digital computing machine must give instructions to interface adapters and receive digital information from them.

 

The project considered both creating and improving previous algorithms and data protocols as controlling the spacecraft. Also creating robust FPGA algorithms and electronics included in the machine

 

Tasks and activities

In this project I took a role of an Electronics Engineer. I was designing FPGAs and digital and analog hardware as well, created PCB schematic and PCB layout. Also I verified the machine using lab instrumentation. Also in my responsibilities there were included preparing and maintaining specifications.

 

ResultsI implemented a memory controller and controller of inter-machines interface also improved the communication between modules in machine on FPGA whcich I sped up in 8 times. I verified the project by writing test benches. Also I designed several circuits for matching elements and realized them on PCBs. I tested them by lab instrumentations (Oscillator, Multimetr).

During this project I gained a lot of practical experience in FPGA (Verilog) programming, PCB schematic and layout  and got some knowledge in design of embedded microprocessors such as 8051 core and Leon 3FT. The project is based on FPGAs from Actel.

 

Applied methods, techniques, tools and hardware

 

Programming Languages    :   Verilog, SystemC

Operating Systems              :   Windows 7.

Applications and Tools        :   Actel Libero IDE, ModelSim, QuestaSim, Cadence (allegro) design toools

Algorithms and protocols    :   Analog Design (DC-DC chips, op amps, transistors, etc); Digital Signal Processing Design, Techniques, and Theory;

                                                  Various hardware protocols: SPI, RS232, MIL-STD-1553-Betc; Robust algorithms, redundancy algorithms (Hamming code)

 


Period                      :           9-2010  -  4-2011

Title                          :“Phobos-Ground” mission

Partners                   :Scientific technical innovation center “TECHCOM”, Moscow, Russia

Role                          :Electronics Engineer

Domain                     :Control system of “Phobos-Ground” mission

Objective                 :Designing interface adapters which

 

Description:

The goal of the project was to create a control system for “Phobos-ground” mission which provide al control signals from launching to landing in Phobos. This project should have researched the surface of Phobos and return samples of ground.  The interface adapters must convert instructions of digital computing machine to devices such as valves, detectors, sensors etc. and back to the computing machines.

 

The project considered both creating and improving signal processing algorithms and data protocols on FPGAs

 

Tasks and activities

In this project I took a role of an Electronics Engineer. I was designing FPGAs (robust signal processing algorithms and protocols. Also I verified the FPGAs by writing testbenches. Also in my responsibilities there were included preparing and maintaining specifications and developing solutions to meet these specifications.I significantly extended my knowledge of algorithms and data structures, as well as my programmer skills.

 

Results

I implemented a few FPGAs working for control of valves, changing an angle of antenna, communication protocols for detectors, ADC, DAC, digital thermometer. I verified the project by writing test benches.  During this project I gained a lot of practical experience in FPGA (Verilog) programming, data protocols and digital signal processing

 

Applied methods, techniques, tools and hardware

 

Programming Languages    :   Verilog, C/C++.

Operating Systems              :   Windows XP.

Applications and Tools        :   Digital Signal Processing Design, Techniques, and Theory;

                                                  Various hardware protocols: SPI, RS232, Manchester code, SpaceWire; Military standards.

 

 


Period                      :9-2009  -  4-2011

Title                          :Communication satellite Yamal 300K

Partners                   :Centre of innovation researches and developments, Federal State Research Institute “Argon”, Moscow, Russia

Role                          :Engineer Designer

Domain                     :Interface unit

Objective                 :PCB designing of interface unit modules

 

Description:

The interface unit of communication satellite Yamal 300K is designed for linking to control blocks as well as to provide computation possibility and digital signal processing.

The focus was to development of new device which combined the computation power of digital computing machine and interface adapters.

 

Tasks and activities

My role was to perform a complete PCB design and then to test the electronics after manufacturing the device. The design cycle included creating the library of eclectronic components (circuits), to model electronic scheme in MultiSim, and then to create n schematic design and complete PCB design. Using lab instruments to test done product. As well as PCB design I was responsible to count the reliability of the device, electrical characteristics and radiation tolerance in theoretical way. During the projects ihad to work with radiation tolerant components meeting military requirements

 

Results

On the project I created six of ten modules and successfully tested them as well. During the project I got a great experience in analog and digital designing, simulation as well as learned two design packages for PCB design. I also gain a lot of theoretical knowledge in electronics and electrotechniks and radition aspects which could effect on the correct work of device.

 

 

Applied methods, techniques, tools and hardware

 

Operating Systems              :   Windows XP Professional

Skills                                    :   Analog Design (DC-DC chips, op amps, transistors, etc); radiation tolerance counting; counting of reliability.

Applications and Tools        :   Cadence design tools (Orcad Pspice, Librarian, Design Entry HDL, PCB editor),P-CAD, Autocad, MultiSim.

 


Period:           1-2010  - 3-2011

Title                          :Development of the module simulator of external relations for checkout equipment adapter interface on FPGA from Actel Company.

Partners                   :Moscow Aviation Institute (State University of Aerospace Technologies), Moscow, Russia and Centre of innovation researches and developments, Federal State Research Institute “Argon”, Moscow, Russia

Role                          :Student

Domain                     :Computers, Computing Complexes and Systems, Networks

Objective                 :Development of the module which provide the computation power for control checking hardware.

 

Description:

Devices designed in the aerospace industry must have guarantees of efficiency. There is a need to check them on the Earth. For this purpose developed control-checking test equipment (CCTE) is designed for automatic control performance of the object and measuring its parameters in the manufacture, testing and maintenance. CCTE should allow not only to carry out the control of individual devices, the adapter interface (AI) at the incoming inspection, acceptance, preliminary and periodic testing, but also to provide emulation of the on-board equipment when working with interface devices. AI provides a computational resource for solving tasks of controlling an engine system, information exchange devices, instruments and sensors.

 

Tasks and activities

In the Diploma project it was developed a module of simulator for AI. A simulator is a compact device that can easily dock with AI and be placed in the same space with the AI during the thermal, thermal vacuum, and other types of tests. The developed module of the simulator combines all the necessary means for testing AI and based on FPGA.

FPGA consists of the following blocks:

1) The controller of commands designed to receive the command of words, words of data from an on-board digital computer and issuing the response data words and status;

2) A programmable memory controller (EEPROM) to implement the SPI-interface of a EEPROM chip. EEPROM is used to determine the rate of exchange on RS232 and to keep some data;

3) The controller WIRE is an implementation of 1-WIRE interface of digital temperature sensor.

4) Code Wagner Transmitter designed for creation data packets from the data buffer to the serial interface. It is used to verify operation of the code Wagner receiver, implemented in AI;

5) Wagner code receiver designed to receive data via the serial interface and recording the results of the reception, as well as to control the buffer of received packets. It is designed for in-device-testing of the Wagner transmitter module;

6) The switch controller which provides the control of keys;

7) Telemetry controller designed to receive power states of devices, electro-pneumatic valves, relays and commands sent by AI.

 

Results

Each controller is implemented using hardware description language Verilog on ProAsic3 from

Actel. Also analogue matching elements were developed. In the work Schematic and PCB designs are done. The proposal of the work was published in the Journal was presented on the conference (see next).

Applied methods, techniques, tools and hardware

 

Programming Languages    :   Verilog

Operating Systems              :   Windows 7.

Applications and Tools        :   P-CAD, Actel Libero IDE, Visio.

Miscellaneous

Invited talks

  • December 2010 “Features of translation from English to Russian and back in manufacturing of aircrafts” at conference organized by Russian Aircraft Corporation “MIG” and Moscow Aviation Institute (Russia, Moscow);
  • September 2010 “Modern technologies of control systems, automatics and information processing”,(Alushta, Russia)

 

Publications:

 

September 2010

Magazine: “Modern technologies of control systems, automatics and information processing”.

Transactions of 19th international scientific and technical workshop.

Topic: “Design of control-checking hardware on the base of programmable logic integrated circuits from Actel.”

 

Awards:

December 2010

Competition: "The best young specialist” in Federal State Research Institute “Argon”, Moscow, Russia

Topic: "Adoption of modern design environments"

Place: Price-winner

 

Language Programs:

Cultural exchange programm –summer 2008 and 2009 (The USA, New Jersey)

 

References upon request

 

Hobbies

  • American Football
  • Basketball
  • Cultures
  • Languages

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