Telecommunications engineer specialized in electronics with an artificial intelligence master. 15 years of multidisciplinary professional experience in digital integrated circuits design (ASIC and FPGA) including experience in system simulation. Knowledge of wide range of computer languages. Availability for work in other locations, fluent in English and Spanish.
Apr/2018 - Now Apple, http://www.apple.com
Company: consumer electronics, computer hardware and software with more than 120k employees worldwide. It has an annual revenue of more than 229000 million USD.
Apr/2018 - Now: ASIC design engineer. Digital verification of mixed signal design with UVM system verilog
Jun/2016 - Mar/2018 ON-semiconductor, http://www.onsemi.com
Company: semiconductor supplier of power and signal management for automotive, consumer, military/aerospace sectors with more than 20k employees worldwide. It has an annual revenue of more than 3000 million USD.
Jun/2016 - Mar/2018 Design engineer
• Design and verification (System Verilog and UVM) for DC-DC controller
• Responsible of communication interfaces: SPI, I2C
• Responsible of design checks: lint, CDC
Sep/2015 - Jun/2016 Intel, http://www.intel.com
Company: semiconductor USA multinational world leader in devices for communication and computing with more than 100k employees worldwide. It has an annual revenue of more than 50000 million USD.
Sep/2015 - Jun/2016 System modelling consultant
• SystemC simulation specification and development with Intel CoFluent
• Scoreboard responsible and develop C++ scoreboard classes
• Responsible of test launching scripts and result analysis
Aug/2010 - Jul/2015 Marvell, http://www.marvell.com
Company: fabless semiconductor USA multinational world leader in consumer electronics with more than 7000 employees worldwide. It ships more than one billion integrated circuits per year with a revenue of more than 3000 million USD.
Mar/2015 - Jul/2015 ASIC engineer
• Member of tape-out sub-project team
• Obtain global view of timing violations: STA (Static Timing Analysis) reportsummarizing from Synopsys Prime-Time reports of multiple modes and corners
• Clock maximum transition time fix with Synopsys ICC
• Multiple checks for ASIC tape-out: clock architecture, pin-out, synthesis warnings, timing violations
• Responsible of internal GUI tool (with tcl/tk) for different front-end and back-end flows
• Responsible of check-list for ASIC tape-out
Jul/2011 - Jul/2015 FPGA engineer
• Responsible of FPGA prototyping sub-project
• Automatize FPGA implementation flow and result analysis as VLSI ASIC prototype: Certify, Synplify and Xilinx ISE
• FPGA platform analysis and selection
• Prototype clock architecture with System Verilog:
– Specify clock architecture for: reuse, easy changes, aligned clocks between
– Generate RTL generic modules for clock generation and buffering
– Generate the RTL of clock architecture: generation, multiplexing and buffering
• Prototype reset architecture with System Verilog:
– Specify reset architecture for reuse existing reset synchronization RTL Verilog modules
– Group clock reset instances for FPGA partitioning
– Generate the RTL for global reset generation and reset for each clock
• Prototype IO ring with System Verilog:
– Specify generic IO modules for: reuse, easy changes and instantiating
– Generate RTL generic modules for IO
– Generate RTL IO-ring grouping clocks by functionality
• Check the RTL with chip level simulation (ncverilog)
• FPGA prototyping with Certify: board and top description, constraint generation for Synopsys tools, design partition to board resources, use of HSTDM connections, assign communication resources between FPGA
• Select board resources and connections between FPGA and external interfaces
• Implementation of FPGA: check the implementation results, modify the design and fix the resource locations
• Prototype physical board integrity check and mount as needed by the design, then, complete the prototype initial start
• This was applied to different G.hn (power-line communications or PLC) projects using HAPS5x (Xilinx Virtex 5 ) and Marvell internal platforms (Xilinx Virtex 6 )
Aug/2010 - Jul/2011 Senior digital design engineer
• Member of ASIC DFT sub-project team
• ASIC JTAG and boundary-scan insertion: select the proprietary JTAG instructions (code, size and meaning), describe the instructions and boundary-scan, run and check the insertion
• ASIC memory BIST insertion: configure the MBIST insertion tool, modify the RTL code
• This was developed once, and the scripts reused for the following projects
• Specify and generate RTL modules for proprietary instructions: load and shift data from configuration registers to JTAG controller and vice versa
• Specify and generate RTL connections for MBIST request and return results as one instruction for all MBIST
• Checked with different chip level simulations (ncverilog) equivalent to ATE runs
Nov/2000 - Aug/2010 Design of Systems on Silicon (DS2), http://www.ds2.es
Company: fabless semiconductor Spanish company with international scope, focused in design of integrated circuit design for high speed power line communications (PLC).
It had more than 140 employees and sales of 20 million USD; it was acquired by Marvell in august of 2010.
2009 - Aug/2010 Senior design engineer
• Member of digital ASIC development team
• Specification, development and verification of HW blocks with System Verilog
• Based in: generic TLM interfaces, use of types, structures and classes
• Specify and prepare generic blocks (interface related utility blocks) and interfaces for RTL design and simulation
• Check the support for different System Verilog high level structures (interfaces and data types) in simulation and synthesis (ASIC and FPGA)
• PLC sub-system (PLC transmission frame generation): design and RTL coding
– Division and specification using generic blocks and interfaces
– Main parts: control, frame calculation and a pipeline for DMA request and frame generation
– Auxiliary queue managers for data consistence
• Sub-system verification conceptual division into different levels of abstraction: from TLM to RTL interfaces. Oriented to DUT + golden model verification
• Development of golden model for the verification
2007 - 2009 System modelling engineer
• Member of design flow improvement team
• Development of high abstraction level environment with SystemC and TLM
• Specification, development and support of simulation environment
• Define TLM communication interfaces and develop the related generic classes
• Define and development of generic blocks
• Technical follow-up of share project with “Universidad de Cantabria”
Jun/2001 - 2007 Design engineer
• Member of digital ASIC development team
• Block description with Verilog: from block specification of proprietary PLC solution, divide the functionality (PLC transmission frame generation) into subblocks, describe each sub-block and perform the connections with Verilog
• Block verification with Verilog: generate a test (bridge related functionality) from the specification, with all combinations of multiple functional parameters, adapt and run the simulation of RTL code and gates
• Functional validation of PLC integrated circuit: initial low level measures (voltage, clocks, power), basic interface checks (clock, timings)
Nov/2000 - Jun/2001 Student in practice (end of studies project)
• Development connection between commercial IP (for PCI bus) and proprietary design with Verilog
• Clock cross domain
2017 Memory BIST insertion with Tessent (32h), http://www.mentor.com
2017 UVM adopter class (32h), http://www.doulos.com
2016 System Verilog for verification specialists (24h), http://www.doulos.com
2016 The Conquest of Space: Space Exploration and Rocket (25h), https://courses.edx.org
2011 - 2015 Master in artificial intelligence at “Universidad Politécnica de Valencia” (UPV), http://www.upv.es/titulaciones/MUIARFID/indexi.html
2012 Personal productivity and management (4 hours) at Fundación tripartita, Alberto Pena
2011 Power reading (4 hours) at Leader building S.L., Sebastian Quirmbach
1994 - 2000 Telecommunication engineer (electronics) at “Universidad Politécnica de Valencia” (UPV), http://www.etsit.upv.es
• Computer languages
– Hardware description: Verilog, System Verilog and SystemC with TLM, VHDL
– Programming: C, FORTRAN, Pascal
– Object oriented programming: C++, Delphi, Java
– Script: Matlab, bash, csh, perl, tcl/tk, sed, awk, GNU-plot
– Planning: CLIPS/COOL, PDDL
– FPGA Xilinx Virtex 5, Xilinx Virtex 6 and HAPS platforms
– FPGA tools and IDE from Synopsys and Xilinx: Certify, Synplify, Identify, ISE
– ASIC synthesis: design-compiler (Synopsys)
– ASIC back-end: prime-time (Synopsys), ICC (Synopsys)
– HDL simulation: ncverilog (Cadence)
– Debug: ddd, multimeter, oscilloscope, logic analyzer
– Lint (for Verilog): spyglass (Attrenta)
– System modelling: CoFluent (Intel)
– Other integrated environments (IDE): repast, SNNS, octave
• Working environment
– Operating system: Linux
– Version control: cvs, git
– Documents and office software: LATEX, office, open office
– English: B2
– Spanish: native
– Catalan: native
Registering is the only way of posting vacancies and obtaining contact details of candidates in our CV database.
All it takes is a few minutes and a credit card (Visa or American Express). To sign-up to this service, simply click on the Register link and fill in the form. You will then have instant access to our system after on-line payment where you will be able to complete the transaction in either US Dollars, UK Pounds or Euros.
All online credit/debit card transitions are handled through our secure third party payment processors at WorldPay. Worldpay are part of The Royal Bank of Scotland Group, the 5th biggest banking group in the world, WorldPay payment solutions are trusted by thousands of businesses, big and small worldwide.
Pricing is €450 (approx £400 or US$450) for one month unlimited job postings and unlimited CV database access (for one user).
If online payment is not convenient, give us a call at +33(0)622757477 or send us an email at email@example.com. We will set up an account for you and invoice you, but in this case, access to our website will be granted only after payment has been received. Note that you can also pay through PayPal.
Please note that the posting of academic positions is free of charge. All you need to do is email us your job description and we will post it for you.
Spacelinks is based in France so the following European Union regulations regarding electronic commerce apply:
- if your business is located outside the EU, VAT does not apply to you
- if your business is located in France, you will be charged a 20% VAT
- if your business is located in the EU and you don't have a valid VAT registration number, you will be charged a 20% VAT
- if your business is located in the EU and you do have a valid VAT registration number, you won't be charged VAT provided you give us your VAT number (mandatory for invoicing)
For sales enquiries and general information, you can call us on +33(0)622757477.
Support is available Mon-Fri on +33(0)622757477 or via email. Out-of-hours support is provided only via email.
Please also note that we are located in France. Our normal office hours are 09:00 to 18:00 Monday to Friday. France timezone is GMT+1.
We are very serious about our job seekers privacy so only legitimate recruiters and employers are eligible for a recruiter account. All subscriptions requests will be manually approved and recruiter accounts constantly monitored. Users who enter inaccurate or incomplete information will not gain access to post jobs or search resumes. Sharing of login details with a third party will result in the suspension of the recruiter's account with no subscription refund.
To ensure you are approved, please include the following on your application:
* The website address of your Company. Under construction websites will be rejected.
* Email - Must end in @yourcompany.com. Applications using free email accounts such as Hotmail, Yahoo or Gmail will be rejected.
Individual exceptions can be made on a case by case basis by emailing firstname.lastname@example.org. Accounts found not to be in compliance will be deleted.