Sr. Systems Validation Engineer (SerDes/Physical Layer)

Sr. Systems Validation Engineer (SerDes/Physical Layer)

MDA Space

Farnborough, United Kingdom

Role:

Reporting to the Chip Validation Team Leader, the candidate will have the following responsibilities:

• Validate high-speed SerDes PHY.
• Execute test plans for:
  • Link bring-up
  • Equalization tuning
• Verify functionality across:
  • PVT (Process, Voltage, Temperature)
  • Different data rates and bandwidths

Lab Bring-up & Measurement:

• Work hands-on with lab equipment:
  • Oscilloscopes (real-time/sampling)
  • BERT (Bit Error Rate Tester)
  • DCA
  • PNAX
• Perform:
  • Eye diagram measurements
  • Jitter tolerance testing
  • Tune PHY parameters
  • Enable debug hooks (register access, logging)
  • Able to test a Stressed eye
• Validation of MDA Chipsets verifying functional and performance metrics
• Development and ownership of chip and system test plan with collaboration of development and test teams
• Development of test automation in Python for the chip and system test plans
• Investigation of root cause of test case failures and providing corrective action in conjunction with the development teams
• Execution, development and planning of Chip & System tests and Contribute to the evolution of product quality for MDA ESMA silicon products
• Support Test Management tools and continuous integration methodologies
• Data analysis and post processing of data collected

Requirements:

• Batchelor/Master Degree in Electronic/Computer Science Engineering
• Experience of testing Telecommunication or Satellite Systems
• Experience of Chip and system testing, especially with Analog, RF and high speed communication blocks
• Knowledge in time domain high speed links (SerDes) and associated equipment (BERT, DCA)
• Proven experience in program language in an automation test environment (C/C++/Python etc.)
• Very good debugging skills. Ability to investigate and root cause the issues observed
• Experience in planning, estimating and development of system tests
• Defect Tracking and Knowledge Management software (Atlassian JIRA and Confluence preferred)
• Knowledge of testing Methodologies
• Knowledge of operation of RF test equipment such as Spectrum Analysers, VNAs/PNA’s, Sig. Gens, power meters , high speed sampling scopes, etc.
• Excellent Interpersonal skills
• Knowledge on RF fundamentals and communications theory
• Independent, self-motivated, team player and multitasking capabilities
• Ability to work in a fast-paced and changing environment