• Specific Tasks:
The post holder will support ASIC and/or FPGA technology developments for R&D and /or projects, supervising that good design practices and manufacturing and test methodologies are applied. In addition, independent verification (through code inspection, simulation and timing analysis) and validation (through HW tests) will have to be carried out for some ASIC and FPGAS developments.
o Provision of VLSI (ASIC & FPGA) technical expertise to Projects involving requirements analysis, performance and budgets analysis, writing and assessment of VLSI specifications; review, evaluation and checking of industrial contractor's VLSI designs. Identification of design deficiencies and problem areas and proposals for their solutions.
o Design, analysis, verification of VLSI systems for control and data processing applications, and/or signal processing using industrial standard tools, hardware description and programming languages.
o When asked to support development contracts regarding the above areas, act as the activity technical responsible, maintain interfaces with the prime contractors, participate in progress meetings and reviews, as requested, and provide appropriate feedback on the achieved progress and discussions.
o When supporting projects, interface with ESA’s project teams, the prime and lower level contractors, participate in progress meetings and reviews, as requested by project work, and provide appropriate feedback on the achieved progress and discussions.
• Specific Competence Requirements:
o Experience in the design of complex microelectronics systems, and familiarity with Industry standard VLSI/ASIC/FPGA CAD tools (e.g. CADENCE, SYNOPSYS, MENTOR, MATLAB, SPW) etc. as well as hardware description languages (VHDL and/or Verilog HDL, SystemC) is essential.
o Being familiar with the Space applications of microelectronics, and having knowledge of Space environment and quality requirements will be an important asset, but it is not mandatory.
o Experience with using third party Intellectual Property (IP) designs (in VHDL and/or SystemC) is a requirement.
o Technical and administrative management of the ESA SystemC and synthesizable VHDL IP Core pool of designs. This work will involve: optimisation, update and overall maintenance and of the ESA VHDL IP Cores databases, provision of technical support to ESA IP Cores users (performing analysis and finding solutions to problems in VHDL code, documentation or design methodology) holding a strong collaboration with our Contracts department in arranging and solving licences and patent issues. Advertising the ESA IP service (website, workshops, etc.), handling IP cores requests and their distribution.