Principal DSP Engineer

Principal DSP Engineer

CesiumAstro

Milton Keynes, United Kingdom

Key responsibilities include:

  • Researching and designing of fast and efficient hardware realisable DSP algorithms to implement functions such as filters, equalisers, timing/carrier recovery loops, multi-rate structures & FFT processing engines;
  • Developing models to provide real-life stimulus for testing the developed algorithms, including phase and Gaussian noise, non-linear RF effects, Doppler, multipath, and other such channel impairments;
  • Developing both floating and fixed point models in MATLAB, Python, and C/C++ to the extent that data from the fixed point model can be directly used to accurately verify the functionality of the VHDL hardware realisation;
  • The successful candidate will be versatile and proactive, a clear communicator and team player with good inter-personal and social skills. They will be capable of generating accurate and concise documentation and design notes, and be able to disseminate critical information and interact with the design team.

Successful candidates will require, as a minimum:

  • 8+ years of postgraduate experience;
  • A strong background in Wireless Communications, with excellent theoretical knowledge of advanced concepts in DSP and digital communication systems, and a detailed understanding of wireless modem design. Knowledge of the real-time implementation of complex DSP in both hardware and software.
  • Strong modelling skills using MATLAB, Python, and C/C++ . Using scripting languages to achieve higher performance and improve testing and productivity through automation;
  • The ability to partition design problems and to define block-level hardware architectures, while optimising the designs for area, speed, and power to meet system requirements. Good knowledge of VHDL is essential;
  • Competence with MS Office tools to present technical information and generate concise reports.

Preferred qualifications:

  • Experience of FPGA development using VHDL, simulation, and top-level integration particularly using Xilinx design tools (Vivado);
  • Good understanding of well-known Wireless Communications standards, in particular the DVB-S2(X), DVB-RCS(2) and CCSDS standards;
  • Understanding of digital and analogue hardware design with some hands-on laboratory experience of bringing-up and validating designs, utilising various lab equipment;
  • Knowledge of VITA-49.2 protocols;
  • Proven track record of on-time and high-quality project delivery;
  • Experience working in both start-up environments as well as larger technical organizations.

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